si511 Silicon Laboratories, si511 Datasheet

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si511

Manufacturer Part Number
si511
Description
Crystal Oscillator Xo 100 Khz To 250 Mhz
Manufacturer
Silicon Laboratories
Datasheet

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C
Features
Applications
Description
The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology
to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO
where a different crystal is required for each output frequency, the Si510/511
uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to
generate any frequency across this range. This IC-based approach allows
the crystal resonator to provide enhanced reliability, improved mechanical
robustness, and excellent stability. In addition, this solution provides superior
supply noise rejection, simplifying low jitter clock generation in noisy
environments. Crystal ESR and DLD are individually production-tested to
guarantee performance and enhance reliability. The Si510/511 is factory-
configurable for a wide variety of user specifications, including frequency,
supply voltage, output format, output enable polarity, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long
lead times and non-recurring engineering charges associated with custom
frequency oscillators.
Functional Block Diagram
Preliminary Rev. 0.9 3/11
Supports any frequency from
100 kHz to 250 MHz
1 ps phase jitter (rms, max)
2 to 4 week lead times
Total stability includes 10-year
aging
Comprehensive production test
coverage includes crystal ESR and
DLD
On-chip LDO regulator for power
supply noise filtering
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
R YS TA L
OE
O
Frequency
Oscillator
SCILLATOR
Fixed
Low Noise Regulator
DSPLL
Any-Frequency
0.1 to 250 MHz
GND
V
®
DD
Synthesis
Copyright © 2011 by Silicon Laboratories
3G-SDI/HD-SDI/SDI
Telecom
Switches/routers
FPGA/ASIC clock generation
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Runt suppression on OE and
power on
Industry standard 5 x 7 and
3.2 x 5 mm packages
Pb-free, RoHS compliant
–40 to 85
(XO) 100 kH
o
C operation
CLK+
CLK–
Z TO
S i 5 1 0 / 5 11
Si510(LVDS/LVPECL/HCSL/
Si511(LVDS/LVPECL/HCSL/
Ordering Information:
2 5 0 M H
GND
GND
GND
GND
OE
NC
NC
OE
OE
NC
OE
Pin Assignments:
Si5602
Si510 (CMOS)
See page 11.
See page 9.
Dual CMOS)
1
2
3
1
2
3
1
2
3
Dual CMOS)
1
2
6
5
4
6
5
4
6
5
4
4
3
Z
V
CLK–
CLK+
V
CLK–
CLK+
V
CLK–
CLK+
V
CLK
DD
DD
DD
DD
Si510

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si511 Summary of contents

Page 1

... OE DD GND 2 3 CLK Si510 (CMOS CLK– GND 3 4 CLK+ Si510(LVDS/LVPECL/HCSL/ Dual CMOS CLK– CLK– GND 3 4 GND 3 4 CLK+ CLK+ Si511(LVDS/LVPECL/HCSL/ Dual CMOS) Si510 ...

Page 2

Si510/511 2 Preliminary Rev. 0.9 ...

Page 3

T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Si510/511 1. Electrical Specifications Table 1. Operating Specifications V = 1.8 V ±5%, 2.5 or 3.3 V ±10 Parameter Symbol Supply Voltage V DD Supply Current "1" Setting "0" Setting V ...

Page 5

Table 2. Output Clock Frequency Characteristics V = 1.8 V ±5%, 2.5 or 3.3 V ±10 Parameter Symbol Nominal Frequency Total Stability Temperature Stability Startup Time T SU Disable Time T D Notes: ...

Page 6

Si510/511 Table 3. Output Clock Levels and Symmetry V = 1.8 V ±5%, 2.5 or 3.3 V ±10 Parameter Symbol CMOS Output Logic V OH High CMOS Output Logic V OL Low CMOS Output Logic I OH ...

Page 7

Table 4. Output Clock Jitter and Phase Noise V = 2.5 or 3.3 V ±10 – Parameter Symbol Period Jitter JPRMS (RMS) Period Jitter JPPKPK (Pk-Pk) Phase Jitter φJ 1.875 MHz to 20 MHz ...

Page 8

Si510/511 Table 5. Absolute Maximum Ratings Parameter Maximum Operating Temperature Storage Temperature Supply Voltage Input Voltage (any input pin) ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile) Soldering Temperature Time at T PEAK Notes: 1. Stresses beyond those listed ...

Page 9

... GND 3 CLK Table 9. Si510 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 2) Pin Name GND 4 CLK+ 5 CLK– Table 10. Si511 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 1) Pin Name GND 4 CLK+ 5 CLK– CLK– ...

Page 10

Si510/511 2.1. Dual CMOS Buffer Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature enables replacement of multiple XOs with a single Si510/11 device Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary ...

Page 11

Ordering Information The Si510/511 supports a wide variety of options including frequency, stability, output format, and V device configurations are programmed into the Si510/511 at time of shipment. Configurations can be specified using the Part Number Configuration chart below. ...

Page 12

... Si510/511 4. Si510/511 Mark Specification Figure 3 illustrates the mark specification for the Si510/511. Use the part number configuration utility located at: to cross-reference the mark code to a specific device configuration. www.silabs.com/VCXOpartnumber 0 = Si510 Si511 CCCCC = mark code TTTTTT = assembly manufacturing code YY = year WW = work week ...

Page 13

Package Outline Diagram mm, 4-pin Figure 4 illustrates the package details for the Si510/511. Table 11 lists the values for the dimensions shown in the illustration.   Table 11. Package Diagram Dimensions ...

Page 14

Si510/511 6. PCB Land Pattern mm, 4-pin Figure 5 illustrates the PCB land pattern for the Si510/511. Table 12 lists the values for the dimensions shown in the illustration. ...

Page 15

Package Outline Diagram mm, 6-pin Figure 6 illustrates the package details for the Si510/511. Table 13 lists the values for the dimensions shown in the illustration.   Figure 6. Si510/511 Outline Diagram Table 13. Package Diagram ...

Page 16

Si510/511 8. PCB Land Pattern mm, 6-pin Figure 7 illustrates the PCB land pattern for the Si510/511. Table 14 lists the values for the dimensions shown in the illustration. Figure 7. Si510/511 PCB ...

Page 17

Package Outline Diagram: 3 mm, 4-pin Figure 8 illustrates the package details for the 3 Si510/511. Table 15 lists the values for the dimensions shown in the illustration.   Table 15. Package Diagram Dimensions ...

Page 18

Si510/511 10. PCB Land Pattern: 3 mm, 4-pin Figure 9 illustrates the 3 PCB land pattern for the Si510/511. Table 16 lists the values for the dimensions shown in the illustration. Figure 9. Si510/511 PCB ...

Page 19

Package Outline Diagram: 3 mm, 6-pin Figure 10 illustrates the package details for the 3 Si510/511. Table 17 lists the values for the dimensions shown in the illustration.   Figure 10. Si510/511 Outline Diagram ...

Page 20

Si510/511 12. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin Figure 11 illustrates the 3.2 x 5.0 mm PCB land pattern for the Si510/511. Table 18 lists the values for the dimensions shown in the illustration.   Figure 11. Si510/511 ...

Page 21

N : OTES Preliminary Rev. 0.9 Si510/511 21 ...

Page 22

... Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages ...

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