si5368 Silicon Laboratories, si5368 Datasheet

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... The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The ...

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... Si5368 Table 1. Performance Specifications (V = 1.8 ±5% or 2.5 V ±10 – º Parameter Symbol Temperature Range T Supply Voltage V Supply Current I DD Input Clock Frequency CK (CKIN1, CKIN2, CKIN3, CKIN4) Input Clock Frequency CK (CKIN3, CKIN4 used as FSYNC inputs) Output Clock Frequency CK (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5 ...

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... IN OUT 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset Phase Noise @ 100 kHz Offset Max spur @ > < 100 MHz) Still Air JA Preliminary Rev. 0.4 Si5368 Min Typ Max Unit 40 — — — – 1.42 — ...

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... Si5368 Table 2. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 kΩ); All pins except CKIN+/CKIN– ESD MM Tolerance; All pins except CKIN+/CKIN– ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN– ...

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... Brick Wall, 100 Hz to 100 MHz SONET_OC48, 12 kHz to 20 MHz SONET_OC192_A, 20 kHz to 80 MHz SONET_OC192_B, 4 MHz to 80 MHz SONET_OC192_C, 50 kHz to 80 MHz Brick Wall, 800 MHz Preliminary Rev. 0.4 100000 1000000 10000000 Jitter, RMS 1,279 fs 315 fs 335 fs 194 fs 318 fs 343 fs Si5368 100000000 5 ...

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... Input Clock V = 3.3 V Sources* DD 130 Ω 130 Ω 82 Ω 82 Ω INC DEC Rate Control Mode (H) Reset *Note: Figure 3. Si5368 Typical Application Circuit (SPI Control Mode Option 1: Option 2: Ferrite Crystal Ext. Refclk 1 µF Bead C 0.1 µF 0.1 µF 1–9 0.1 µF CKIN1+ CKOUT1+ CKIN1– ...

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... The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range ...

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... Pin # Pin Name I 20, NC 22, 23, 24, 25, 37, 47, 48, 50, 51, 52, 53, 56, 66, 67, 72, 73, 74, 75, 80, 85 RST I Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map Si5368 ...

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... C1B O 10 C2B O 11 C3B O 12 INT_ALM O Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. Supply The device operates from a 1.8 or 2.5 V supply. Bypass capaci- tors should be associated with the following V Pins Bypass Cap 5, 6 0.1 µF 15 0.1 µ ...

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... CKIN4– 32 RATE0 I 42 RATE1 Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. 10 Signal Level LVCMOS Input Clock Select/CKIN3 or CKIN4 Active Clock Indicator. Input: If manual clock selection is chosen, and if CKSEL_PIN = 1, the CKSEL pins control clock selection and the CKSEL_REG bits are ignored ...

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... CKIN1– 49 LOL O 54 DEC I Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. MULTI Clock Input 2. Differential input clock. This input can also be driven with a sin- gle-ended signal. MULTI Clock Input 3. Differential clock input. This input can also be driven with a sin- gle-ended signal ...

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... A2_SS I Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. 12 Signal Level LVCMOS Coarse Latency Increment. A pulse on this pin increases the input to output device latency by 1/fOSC (approximately 200 ps). Detailed operations, restric- tions, and timing characteristics for this pin may be found in the Any-Rate Precision Clock Family Reference Manual ...

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... CKOUT4– CKOUT4+ GND PAD GND PAD GND Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. LVCMOS Serial Data In. In SPI microprocessor control mode (CMODE = 1), this pin functions as the serial data input microprocessor control mode (CMODE = 0), this pin is ignored ...

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... Output Clock Number Frequency Range Si5368A-C-GQ 2 kHz–945 MHz 970–1134 MHz 1.213–1.417 GHz Si5368B-C-GQ 2 kHz–808 MHz Si5368C-C-GQ 2 kHz–346 MHz 14 Package ROHS6, Pb-Free 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP Preliminary Rev. 0.4 ...

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... Package Outline: 100-Pin TQFP Figure 4 illustrates the package details for the Si5368. Table 4 lists the values for the dimensions shown in the illustration. Figure 4. 100-Pin Thin Quad Flat Package (TQFP) Table 4. Dimension Min Nom A — A1 0.05 A2 0.95 1.00 b 0.17 0.22 c 0.09 D 16.00 BSC. D1 14.00 BSC. D2 3.85 4.00 e 0.50 BSC. Notes: 1 ...

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... Si5368 5. Recommended PCB Layout 16 Figure 5. PCB Land Pattern Diagram Preliminary Rev. 0.4 ...

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... Notes (Card Assembly No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Preliminary Rev. 0.4 MIN MAX 0.50 BSC. 15.40 REF. 15.40 REF. 3.90 4.10 3.90 4.10 13.90 — 13.90 — — 0.30 1.50 REF. — 16.90 — 16.90 0.15 REF — 1.00 Si5368 17 ...

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... Revision 0.3 to Revision 0.4 Changed V specification for 1 Updated Table 1 on page 2. Updated Table 2 on page 4. Added table under Figure 1 on page 5. Updated "1. Functional Description" on page 7. Clarified "2. Pin Descriptions: Si5368" on page 8 including correcting pin assignments for RATE0 and RATE1. 18 Preliminary Rev. 0.4 ...

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... N : OTES Preliminary Rev. 0.4 Si5368 19 ...

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... Si5368 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...