si5319 Silicon Laboratories, si5319 Datasheet - Page 7

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si5319

Manufacturer Part Number
si5319
Description
Any-rate Precision Clock Multiplier/jitter Attenuator
Manufacturer
Silicon Laboratories
Datasheet

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2. Pin Descriptions: Si5319
Pin numbers are preliminary and subject to change.
Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
2, 4, 9,
12–14,
33–35
Pin #
30,
1
3
Pin Name
INT_CB
RST
NC
I/O
O
I
Signal Level
LVCMOS
LVCMOS
INT_CB
GND
VDD
RST
NC
NC
XB
NC
XA
1
2
3
4
5
6
7
8
9
External Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state and forces the device regis-
ters to their default value. Clock outputs are disabled during reset. The
part must be programmed after a reset or power-on to get a clock out-
put. See Family Reference Manual for details.
This pin has a weak pull-up.
No Connect.
This pin must be left unconnected for normal operation.
Interrupt/CKIN Invalid Indicator.
This pin functions as a device interrupt output or an alarm output for
CKIN. If used as an interrupt output, INT_PIN must be set to 1. The pin
functions as a maskable interrupt output with active polarity controlled
by the INT_POL register bit.
If used as an alarm output, the pin functions as a LOS alarm indicator
for CKIN. Set CK_BAD_PIN = 1 and INT_PIN = 0.
0 = CKIN present.
1 = LOS on CKIN.
The active polarity is controlled by CK_BAD_POL. If no function is
selected, the pin tristates.
36
10 11 12 13 14 15 16 17
35
Preliminary Rev. 0.3
34
33
GND
Pad
32
31
30
29
28
18
27
26
25
24
23
22
21
20
19
SDI
A2_SS
A1
A0
SDA_SDO
SCL
CS
GND
GND
Description
Si5319
7

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