sc9821c Silan, sc9821c Datasheet - Page 6

• Manufacturer Part Number: sc9821c
• Description: Cd Electronic Shockproof Controller
• Manufacturer: Silan

HANGZHOU SILAN MICROELECTRONICS CO.,LTD
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1.1. 2 Serial communication protocol processing
the data. The transmission process of one frame is as followed:
transmitting data; the leading Ack is may be given to Guest by Host(Customers address check all mode
common), and may be fed back by Guest. That is all decided by the information of Command pack.
8 bits of Command byte are as followed:
Start Signal:
Data Signal:
Ack:
EndSignal:
Read/Write:
Burst:
Reset:
AddrExtend:
Read/Write
Host and Guest realize the communication between each other by different explanation and processing for
In the above figure, Command pack explains the type of the frame; Addr is 8-bit address length. Data is the
Command: In the process of the whole protocol processing, the Command pack byte is critical.
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Bit7
Burst
Start of frame
We define the first checking low level of DataAvail at the rising edge of SsiSClk at Guest
port as the start of frame. When check the start signal, the guest can receive the data at
the next rising edge.
Data signal
Data signal bit width sent by host computer is one SsiSClk clock cycle.
Feedback signal
1. When Guest port receives the right addressing data, it feeds back to Host signal. And
the width is an SsiSClk cycle. Used for data lead avoiding unmatched signal between two
rising edges or corresponding to the data feedback to Host.
2. When Host sends to all Guest ports, signal before sending data is as lead signal, and
between two falling edges of SsiSClk.
End of frame
When Guest detects the DataAvail at rising edge of SsiSClk, it means the transmission is
end and waits for the next one.
Bit6
Read-write flag bit; 1 denotes read data from Guest to Host, and 0 denotes the data
flow is from Host to Guest.
Cooperate with Reset
When Burst is 0, reset is 1, denotes appointed Guest reset, at this time, have no next
byte; When Burst and Reset are 1 at the same time, denotes short command form.
The form of short command is introduced in “ short command register” .
1 denotes this operation based on 16-bit address mode, and high 8-bit follows the low
8-bit; 0 is default 8-bit address operation mode.
Reset
Bit5
Figure 1 SSI frame signal format
AddrExtend
Bit4
Address[3]
Bit3
Address[2]
Bit2
Address[1]
REV:1.0
Bit1
SC9821C
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Address[0]
2006.07.21
Bit0