IDT74FCT823CTSOG8 IDT, Integrated Device Technology Inc, IDT74FCT823CTSOG8 Datasheet - Page 2

• Manufacturer Part Number: IDT74FCT823CTSOG8
• Description: IC REGISTER 9BIT CLR/3ST 24-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 74FCTr
• Type: D-Type Busr

Specifications of IDT74FCT823CTSOG8

• Function: Master Reset
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 9
• Delay Time - Propagation: 1.5ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 15mA, 48mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Frequency - Clock: -
• Other names: 74FCT823CTSOG8

PIN DESCRIPTION
PIN CONFIGURATION
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
Pin Names
CLR
C P
OE
Dx
Y x
EN
GND
CLR
I/O
O
OE
I
I
I
I
I
D
D
D
D
D
D
D
D
D
0
1
2
3
4
5
6
7
8
D Flip-Flop Data Inputs
When the clear input is LOW and OE is LOW, the
Qx outputs are LOW. When the clear input is HIGH,
data can be entered into the register.
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Register 3-State Outputs
Clock Enable. When the clock enable is LOW, data
on the Dx output is transferred to the Qx output on the
LOW-to-HIGH transition. When the clock enable is
HIGH, the Qx outputs do not change state, regardless
of the data or clock input transitions.
Output Control. When the OE is HIGH, the Yx
outputs are in the high-impedance state. When the
OE is LOW, the TRUE register data is present at the
Yx outputs.
1
2
3
4
5
6
7
8
9
10
11
12
SOIC/ QSOP
TOP VIEW
23
20
19
18
17
16
15
14
13
24
22
21
Description
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
EN
CP
CC
2
3
4
5
6
7
0
1
8
2
FUNCTION TABLE
NOTE:
1. H = HIGH Voltage Level
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
NOTE:
1. This parameter is measured at characterization but not tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Symbol
C
C
Symbol
V
V
T
I
OUT
X = Don’t Care
L = LOW Voltage Level
NC = No Change
↑ = LOW-to-HIGH Transition
Z = High Impedance
STG
TERM
TERM
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
IN
OUT
OE
H
H
H
H
H
H
L
L
L
L
(2)
(3)
CLR
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
H
H
H
H
H
H
H
H
L
L
Input Capacitance
Output Capacitance
Parameter
Inputs
EN
H
H
L
L
X
X
L
L
L
L
Description
(1)
Dx
H
H
H
X
X
X
X
L
L
L
(T
A
INDUSTRIAL TEMPERATURE RANGE
CP
= +25°C, F = 1.0MHz)
↑
↑
↑
↑
↑
↑
X
X
X
X
(1)
Conditions
V
V
OUT
IN
= 0V
= 0V
N C
N C
Qx
H
H
H
L
L
L
L
L
Internal/
Outputs
N C
–0.5 to V
Yx
H
Typ.
Z
Z
Z
L
Z
Z
Z
L
–65 to +150
–60 to +120
6
8
–0.5 to +7
Max
CC
Function
Max.
+0.5
10
12
High Z
Clear
Hold
Load
(1)
Unit
Unit
pF
pF
mA
° C
V
V