IDT74ALVCH162374PAG IDT, Integrated Device Technology Inc, IDT74ALVCH162374PAG Datasheet

IDT74ALVCH162374PAG

Manufacturer Part Number

IDT74ALVCH162374PAG

Description

IC FLIP FLOP 16BIT D 3ST 48TSSOP

Manufacturer

IDT, Integrated Device Technology Inc

Series

74ALVCHr

Type

D-Typer

Datasheet

1.IDT74ALVCH162374PAG8.pdf (6 pages)

Specifications of IDT74ALVCH162374PAG

Function

Standard

Output Type

Tri-State Non Inverted

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

150MHz

Delay Time - Propagation

1ns

Trigger Type

Positive Edge

Current - Output High, Low

12mA, 12mA

Voltage - Supply

2.3 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74ALVCH162374PAG

Available stocks

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Manufacturer

Quantity

Price

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Bonase Electronics (HK) Co., Limited

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FEATURES:

• 0.5 MICRON CMOS Technology

• Typical t

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

• V

• CMOS power levels (0.4μ μ μ μ μ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP package

DRIVE FEATURES:

• Balanced Output Drivers: ±12mA

• Low switching noise

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

FUNCTIONAL BLOCK DIAGRAM

IDT74ALVCH162374

3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

CLK

machine model (C = 200pF, R = 0)

= 3.3V ± 0.3V, Normal Range

= 2.7V to 3.6V, Extended Range

= 2.5V ± 0.2V

SK(o)

(Output Skew) < 250ps

TO 7 OTHER CHANNELS

3.3V CMOS 16-BIT EDGE-

TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

AND BUS-HOLD

DESCRIPTION:

CMOS technology. The ALVCH162374 is particularly suitable for implementing

buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can

be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of

the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up

at the data (D) inputs. OE can be used to place the eight outputs in either a normal

logic state (high or low logic levels) or a high-impedance state. In the high-

impedance state, the outputs neither load nor drive the bus lines significantly.

The high-impedance state and the increased drive provide the capability to

drive bus lines without need for interface or pullup components. OE does not

affect internal operations of the flip-flop. Old data can be retained or new data

can be entered while the outputs are in the high-impedance state.

will significantly reduce line noise when used with light loads. This driver has

been designed to drive ±12mA at the designated threshold levels.

whenever the input goes to a high impedance. This prevents floating inputs and

eliminates the need for pull-up/down resistor.

CLK

This 16-bit edge-triggered D-type flip-flop is built using advanced dual metal

The ALVCH162374 has series resistors in the device output structure which

The ALVCH162374 has “bus-hold” which retains the inputs’ last state

TO 7 OTHER CHAN-

NELS

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH162374

JULY 2009

DSC-4565/5

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IDT74ALVCH162374PAG Summary of contents

Page 1

IDT74ALVCH162374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP FEATURES: • 0.5 MICRON CMOS Technology • Typical t (Output Skew) < 250ps SK(o) • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF ...

Page 2

IDT74ALVCH162374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP PIN CONFIGURATION GND ...

Page 3

IDT74ALVCH162374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input LOW Voltage Level ...

Page 4

IDT74ALVCH162374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP OUTPUT DRIVE CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL NOTE and V must be within the min. or max. range shown in the DC ELECTRICAL ...

Page 5

IDT74ALVCH162374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 300 300 LZ ...

Page 6

IDT74ALVCH162374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP ORDERING INFORMATION XX ALVC X XX Temp. Range Bus-Hold Family CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XX XXX Device Type Package PAG Thin Shrink Small Outline Package - ...

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