st10f269z1 STMicroelectronics, st10f269z1 Datasheet - Page 163

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st10f269z1

Manufacturer Part Number
st10f269z1
Description
St10f269 16-bit Mcu With Mac Unit, 256k Byte Flash Memory And 12k Byte Ram
Manufacturer
STMicroelectronics
Datasheet

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ST10F269
Notes: 1. RW-delay and
3. Partially tested, guaranteed by design characterization.
t
t
t
t
t
t
t
t
48
49
50
51
53
68
55
57
Symbol
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes before the end of RD have no impact on read cycles.
CC
CC
CC
SR
SR
SR
CC
CC
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
t
A
refer to the next following bus cycle.
Parameter
3
3
36.875 + t
21.25 + t
17.25 + t
1.625 + t
Minimum
Maximum CPU Clock =
-10 + t
0
F
C
C
F
32MHz
C
Maximum
21.25 + t
0 + t
F
F
2TCL - 10 + t
3TCL - 10 + t
2TCL - 14 + t
TCL - 14 + t
Minimum
-10 + t
1/2 TCL = 1 to 32MHz
Variable CPU Clock
0
F
F
C
C
C
2TCL - 10 + t
TCL - 10 + t
Maximum
F
F
163/184
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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