mach435 Lattice Semiconductor Corp., mach435 Datasheet - Page 6

• Manufacturer Part Number: mach435
• Description: High-density Ee Cmos Programmable Logic
• Manufacturer: Lattice Semiconductor Corp.

The Macrocell and Output Switch Matrix
The MACH435 has 16 macrocells, half of which can
drive I/O pins; this selection is made by the output switch
matrix. Each macrocell can drive one of four I/O cells.
The allowed combinations are shown in Table 2. Please
refer to Figure 1 for macrocell and I/O pin numbers.
6
Macrocell
Table 2. Output Switch Matrix Combinations
M0, M1
M2, M3
M4, M5
M6, M7
M8, M9
M10, M11
M12, M13
M14, M15
I/O Pin
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Macrocell
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
Table 1. Logic Allocation
I/O5, I/O6, I/O7, I/O0
I/O6, I/O7, I/O0, I/O1
I/O7, I/O0, I/O1, I/O2
I/O0, I/O1, I/O2, I/O3
I/O1, I/O2, I/O3, I/O4
I/O2, I/O3, I/O4, I/O5
I/O3, I/O4, I/O5, I/O6
I/O4, I/O5, I/O6, I/O7
M0, M1, M2, M3, M4, M5, M6, M7
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M14, M15, M0, M1, M2, M3, M4, M5
Available Macrocells
Routable to I/O Pins
C0, C1, C2
C0, C1, C2, C3
C1, C2, C3, C4
C2, C3, C4, C5
C3, C4, C5, C6
C4, C5, C6, C7
C5, C6, C7, C8
C6, C7, C8, C9
C7, C8, C9, C10
C8, C9, C10, C11
C9, C10, C11, C12
C10, C11, C12, C13
C11, C12, C13, C14
C12, C13, C14, C15
C13, C14, C15
C14, C15
Available Clusters
MACH435-12/15/20, Q-20/25
The macrocells can be configured as registered,
latched, or combinatorial. In combination with the logic
allocator, the registered configuration can be any of the
standard flip-flop types. The macrocell provides internal
feedback whether configured with or without the flip-
flop, and whether or not the macrocell drives an I/O cell.
The flip-flop clock depends on the mode selected for
the macrocell. In synchronous mode, any of the PAL
block clocks generated by the Clock Generator can be
used. In asynchronous mode, the additional choice of
either edge of an individual product-term clock is
available.
Initialization can be handled as part of a bank of
macrocells via the PAL block initialization terms if in
synchronous mode, or individually if in asynchronous
mode. In synchronous mode, one of the PAL block
product terms is available each for preset and reset. The
swap function determines which product term drives
which function. This allows initialization polarity com-
patibility with the MACH 1 and 2 series. In asynchronous
mode, one product term can be used either to drive reset
or preset.
The I/O Cell
The I/O cell in the MACH435 consists of a three-state
buffer and an input flip-flop. The I/O cell is driven by one
of the macrocells, as selected by the output switch
matrix. Each I/O cell can take its input from one of eight
macrocells. The three-state buffer is controlled by an
individual product term. The input flip-flop can be
configured as a register or latch. Both the direct I/O
signal and the registered/latched signal are available to
the input switch matrix, and can be used simultaneously
if desired.