sm5953a Nippon Precision Circuits Inc, (NPC), sm5953a Datasheet - Page 11

• Manufacturer Part Number: sm5953a
• Description: Surround Effects Processor Lsi
• Manufacturer: Nippon Precision Circuits Inc, (NPC)

SM5953A
Direct Mute (DMUTE Flag)
The SM5953A can directly mute the outputs by setting the microcontroller interface DMUTE flag to 1. In
direct muting, the outputs are muted starting from the word synchronized to the next ZLRCK clock rising edge
after the DMUTE flag is set to 1. Similarly, direct muting is released starting from the word synchronized to the
next ZLRCK clock rising edge after the DMUTE flag is set to 0. When direct muting is selected, the device is
simultaneously initialized and delay memory data is cleared. The initialization operation takes 128/fs time
(2.902ms @ 44.1kHz).
Power-Down (PDN Pin and PDN Flag)
The SM5953A can power-down either by setting the PDN input LOW or by setting the microcontroller inter-
face PDN flag to 0. At power-down, all circuit internal signals stop (with the exception of the microcontroller
interface circuits) and the outputs are tied LOW to suppress power consumption. When power-down is selected
or released, the system outputs should also be muted to prevent noise from occurring. Power-down should be
selected only after muting is selected, and muting should be released only after power-down is released. When
power-down is released, the initialization sequence becomes active and all internal SRAM data is cleared. The
YLRCK, YSCK, and CLK input clocks must also be supplied and stable for the initialization sequence to oper-
ate when power-down is released.
Through-Mode (THRUN Pin and THRUN Flag)
The SM5953A can take the input signals (YLRCK, YSCK, YSRDATA) and pass them directly to the outputs
(ZLRCK, ZSCK, ZSRDATA) either by setting the THRUN input LOW or by setting the microcontroller inter-
face THRUN flag to 0. In through mode, all circuits stop (except for the connection from inputs to outputs and
the microcontroller interface), reducing the power consumption to a minimum. When returning from through
mode to normal mode of operation, the initialization sequence for all circuits becomes active and internal
SRAM data is cleared. The YLRCK, YSCK, and CLK input clocks must also be supplied and stable for the ini-
tialization sequence to operate when through mode is released.
Note: When switching between through mode and normal mode, YLRCK and ZLRCK become discontinuous
and an output noise may occur. Consequently, the system outputs should be muted.
System Reset (RSTN Pin)
At power-ON, the SM5953A must be reset. The device is reset by applying a LOW-level pulse on the RSTN
input. When the supply voltage is stable and the YLRCK, YSCK, CLK clocks are stable, system reset is
released by taking RSTN from LOW to HIGH. If YLRCK, YSCK, or CLK stop during normal operation, a sys-
tem reset must be performed after the clocks have restabilized. When the system reset is released, the initializa-
tion sequence operates and the internal SRAM data is cleared. The initialization operation takes 128/fs time
(2.902ms @ 44.1kHz).
SEIKO NPC CORPORATION —11