sm5876 Nippon Precision Circuits Inc, (NPC), sm5876 Datasheet - Page 13

• Manufacturer Part Number: sm5876
• Description: 3rd-order, 2-channel D/a Converter
• Manufacturer: Nippon Precision Circuits Inc, (NPC)

FUNCTIONAL DESCRIPTION
System Clock/Speed Switching (XTI, XTO, CKO, CKSL)
The system clock on XTI can be set to run at one of
two speeds, 384fs (normal speed) or 768fs (double-
speed), where fs is the input frequency on LRCI. The
speed for CD playback is set by the input level on
CKSL, as shown in table 1.
Table 1. System clock select
System Reset (RSTN)
The device should be reset in the following cases.
Output mute
At power-ON reset (when RSTN goes LOW), the
outputs LO (LON) and RO (RON) enter the output
mute state. Mute is released on the 9th LRCI rising
edge after RSTN goes HIGH. During this cycle, the
timing reset can cause output noise to be generated.
XTI input clock
frequency
CD playback XTI
frequency
CKO output clock
frequency
Internal system
clock period
At power ON
When LRCI and/or the system clock XTI stop, or
other abnormalities occur.
When switching the XTI clock 768fs
Parameter
RO(RON)
LO(LON)
RSTN
Internal
LRCI
Reset
Symbol
(= 1/t
T
f
CO
SYS
f
f
XI
XI
XI
)
33.8688 MHz
at fs = 44.1
HIGH
768fs
768fs
kHz
2t
Low
XI
CKSL
1
Figure 1. System reset timing
16.9344 MHz
at fs = 44.1
384fs.
LOW
384fs
384fs
kHz
t
XI
2
SM5876AM
Output Muted
3
Note that the input clock accuracy and signal-to-
noise ratio greatly influence the AC analog character-
istics. Accordingly, care should be taken to ensure
that the clock is free from jitter.
The system clock can be controlled by a crystal
oscillator comprising a crystal connected between
XTI and XTO and the built-in CMOS inverter. Alter-
natively, an external system clock can be input on
XTI. As the internal CMOS inverter has a feedback
resistor, the external clock can be AC coupled to
XTI. The system clock is output on CKO.
The device is reset by applying a LOW-level pulse on
RSTN. At system reset, the internal arithmetic opera-
tion and output timing counter are synchronized on
the next LRCI rising edge, as shown in figure 1.
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