fm3808 Ramtron Corporation, fm3808 Datasheet - Page 5

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fm3808

Manufacturer Part Number
fm3808
Description
256kb Bytewide Fram W/ Real-time Clock
Manufacturer
Ramtron Corporation
Datasheet

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Rev. 1.3 (EOL)
Feb. 2006
/OSCEN
Reserved
CALS
CAL.3-0
7FF7h
WDS
/WDW
WDT.5-0
7FF6h
WIE
AIE
PFE
ABE
H/L
P/L
7FF5h
/M
Address
7FF4h
/M
7FF3h
/Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling
the oscillator saves battery power during storage. On a no-battery power up, this bit is set to 1. The
RTC will not run until the oscillator is enabled. Set this bit to 0 to activate the RTC.
Do not use. Should remain set to 0.
Calibration sign. Determines if the calibration adjustment is applied as an addition to or as a subtraction
from the time-base. This bit is implemented in FRAM. Calibration is explained below
These four bits control the calibration of the clock. These bits are implemented in FRAM.
Watchdog Timer
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no
affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is write only.
Reading it always will return a 0.
Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT.5-0) so it cannot
be written. This allows the user to strobe the watchdog without disturbing the timeout value. Setting this
bit to 0 allows bits 5-0 to be written on the next write to the Watchdog register. The new value will be
loaded on the next internal watchdog clock after the write cycle is complete. This function is explained
in more detail in the watchdog Timer section below.
Watchdog Timeout selection. The watchdog timer interval is selected by the 6-bit value in this register.
It represents a multiplier of the 32 Hz count (31.25 ms). The minimum range or timeout value is 31.25
ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3Fh). Setting the watchdog timer
register to 0 disables the timer. These bits can be written only if the /WDW bit was cleared to 0 on a
previous cycle.
Interrupts
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives
the INT pin as well as the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When
set to 0, the alarm match only affects the AF flag.
Power-Fail Enable. When set to 1, the power-fail monitor drives the pin as well as the PF flag. When set
to 0, the power-fail monitor affects only the PF flag.
Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function
even in battery backup mode. When set to 0, the alarm will occur only when VDD>VLO.
High/Low. When set to a 1, the INT pin is push/pull active high. When set to a 0, the INT pin is open
drain, active low.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source
for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until
the Flags/Control register is read.
Alarm – Date of the month
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the date value.
Description
Alarm – Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match: Setting this bit to 0 causes the Hours value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the Hours value.
Alarm – Minutes
WDS
WIE
D7
D7
D7
D7
D7
M
M
M
10 min.2
WDW
AIE
D6
D6
D6
D6
D6
0
0
10 hours.1
10 date.1
10 min.1
WDT.5
PFE
D5
D5
D5
D5
D5
10 hours.0
10 date.0
10 min.0
WDT.4
ABE
D4
D4
D4
D4
D4
Hours.3
WDT.3
Date.3
Min.3
H/L
D3
D3
D3
D3
D3
WDT.2
Hours2
Date.2
Min.2
P/L
D2
D2
D2
D2
D2
Reserved
Hours.1
WDT.1
Date.1
Min.1
D1
D1
D1
D1
D1
Reserved
Hours.0
Page 5 of 27
WDT.0
Date.0
Min.0
FM3808
D0
D0
D0
D0
D0

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