fm3204 Ramtron Corporation, fm3204 Datasheet - Page 5

• Manufacturer Part Number: fm3204
• Description: Integrated Processor Companion With Memory
• Manufacturer: Ramtron Corporation

The bits VTP1 and VTP0 control the trip point of the
low voltage detect circuit. They are located in register
0Bh, bits 1 and 0.
The watchdog timer can also be used to assert the
reset signal (/RST). The watchdog is a free running
programmable timer. The period can be software
programmed from 100 ms to 3 seconds in 100 ms
increments via a 5-bit nonvolatile register. All
programmed settings are minimum values and vary
with
specifications. The watchdog has two additional
controls associated with its operation, a watchdog
enable bit (WDE) and timer restart bits (WR). Both
the enable bit must be set and the watchdog must
timeout in order to drive /RST active. If a reset event
occurs, the timer will automatically restart on the
rising edge of the reset pulse. If not enabled, the
watchdog timer runs but has no effect on /RST. Note
that setting the maximum timeout setting (11111b)
disables the counter to save power. The second
control is a nibble that restarts the timer preventing a
reset. The timer should be restarted after changing the
timeout value.
The watchdog timeout value is located in register
0Ah, bits 4-0, and the watchdog enable is bit 7. The
watchdog is restarted by writing the pattern 1010b to
the lower nibble of register 09h. Writing this pattern
will also cause the timer to load new timeout values.
Writing other patterns to this address will not affect
its operation. Note the watchdog timer is free-
running. Prior to enabling it, users should restart the
timer as described above. This assures that the full
timeout period will be set immediately after enabling.
The watchdog is disabled when V
The following table summarizes the watchdog bits. A
block diagram follows.
Watchdog timeout
Watchdog enable
Watchdog restart
Rev. 2.4
Mar. 2008
Timebase
temperature
V
2.6V
2.9V
3.9V
4.4V
TP
100 ms
Figure 3. Watchdog Timer
clock
according
Watchdog
Counter
WDT4-0
WR3-0 = 1010b to restart
WDE
WR3-0
timeout
VTP1
0
0
1
1
VTP0
to
0
1
0
1
0Ah, bits 4-0
0Ah, bit 7
09h, bits 3-0
DD
WDE
the
is below V
operating
/RST
TP
.
Figure 5. Comparator as Early Power-Fail Warning
Manual Reset
The /RST pin is bi-directional and allows the
FM32xx to filter and de-bounce a manual reset
switch. The /RST input detects an external low
condition and responds by driving the /RST signal
low for 100 ms.
Note that an internal weak pull-up on /RST
eliminates
components.
Reset Flags
In case of a reset condition, a flag will be set to
indicate the source of the reset. A low V
manual reset is indicated by the POR flag, register
09h bit 6. A watchdog reset is indicated by the WTR
flag, register 09h bit 7. Note that the flags are
internally set in response to reset sources, but they
must be cleared by the user. When the register is
read, it is possible that both flags are set if both have
occurred since the user last cleared them.
Early Power Fail Comparator
An early power fail warning can be provided to the
processor well before V
comparator is used to create a power fail interrupt
(NMI). This can be accomplished by connecting the
PFI pin to the unregulated power supply via a resistor
divider. An application circuit is shown below.
NMI input
To MCU
Behavior
Switch
RST
CAL/PFO
MCU
the
Reset
Switch
Figure 4. Manual Reset
FM32xx
FM32xx
need
+
-
drives
1.2V ref
RST
DD
for
100 ms
drops out of spec. The
FM32xx
PFI
additional
Regulator
FM3204/16/64/256
DD
Page 5 of 22
external
reset or
VDD