ad6435 Analog Devices, Inc., ad6435 Datasheet - Page 8

• Manufacturer Part Number: ad6435
• Description: Adsl Shipset
• Manufacturer: Analog Devices, Inc.

This Material Copyrighted By Its Respective Manufacturer
AD6435
CO/RT INTERFACE TIMING
Simplex Serial Port
The simplex serial port consists of four pins, two outputs,
SIMPLX_RX and SIMPLX_CLKO, and two inputs, SIMPLX_
TX and SIMPLX_CLKI. The serial clock rate is completely
variable between 8 kbps and 12.288 Mbps. The interface
operates differently at the CO and RT locations.
Parameter
t
t
t
t
At the CO, the two input pins SIMPLX_TX and SIMPLX_CLKI
are used while the two output pins SIMPLX_RX and SIMPLX_
CLKO are not functionally connected. The interface can oper-
ate at a continuous data stream into SIMPLX_RX at a fixed
frequency between 8 kbps and 12.288 Mbps. The data rate is
set while the DTIR is in reset and does not change without
going into the reset state again.
At the RT, the two output pins SIMPLX_RX and SIMPLX_
CLKO are used while the two input pins SIMPLX_TX and
SIMPLX_CLKI are not functionally connected. The interface can
operate at a continuous data stream out of SIMPLX_RX at a
fixed frequency between 8 kbps and 12.288 Mbps. The data
rate is set while the DTIR is in reset and does not change with-
out going into the reset state again.
For the Simplex Rx channel, data is driven out of the AD6435
on the positive edge of the respective CLKO signal and should
be sampled by the external circuit on the negative edge.
For the Simplex Tx channel, the data is sampled by the AD6435
on the positive edge of the respective CLKO signal and should
be driven by the external circuit on the negative edge.
Duplex Serial Port
The duplex serial port consists of four pins, two outputs,
DUPLX_RX and DUPLX_CLKO, and two inputs, DUPLX_TX
SRX-S
SRX-H
STX-S
STX-H
SIMPLX_CLKI
SIMPLX_TX
SIMPLX_CLKO
SIMPLX_RX
CO XMT
Figure 3. Simplex Serial Port
Table II. TX Serial I/F Timing
t
Description
Setup Time of SIMPLX_RX from
Falling Edge of SIMPLX_CLKO
Hold Time of SIMPLX_RX from
Falling Edge of SIMPLX_CLKO
Setup Time of SIMPLX_TX from
Rising Edge of SIMPLX_CLKI
Hold Time of SIMPLX_TX from
Rising Edge of SIMPLX_CLKI
STX-S
VALID DATA
DTIR XMT
DTIR RECEIVE
t
SRX-S
t
STX-H
VALID DATA
RT RECEIVE
t
SRX-H
Typ
5 ns
5 ns
5 ns
5 ns
–8–
and DUPLX_CLKI. The serial clock rate is completely variable
between 8 kbps and 4.096 Mbps. The interface operates identi-
cally at the CO and RT locations. The input interface can ac-
cept a continuous stream of data at a fixed frequency within the
duplex rate. The output interface on the other end transmits the
same continuous stream of data at the same fixed frequency.
This frequency is established and programmed into the registers
by the DSP during reset.
For the Duplex Rx channel, data is driven out of the AD6435
on the positive edge of the respective CLKO signal and should
be sampled by the external circuit on the negative edge.
For the Duplex Tx channel, the data is sampled by the AD6435
on the positive edge of the respective CLKO signal and should
be driven by the external circuit on the negative edge.
Parameter
t
t
t
t
INTERLEAVE RAM INTERFACE
The DTIR (DIA) Interfaces an external 32k 8 Interleave
RAM. The interleave RAM interface consists of M_A(14:0),
M_D(7:0), NM_WE, and NM_OE. When operating at 3.3 V
RAM must have access time less than 50 ns. For further infor-
mation concerning the operation of the RAM access, consult the
DIA specification.
DME INTERFACE TIMING
All signals transmitted by the DME to the DTIR are transmit-
ted on the rising edge and sampled on the falling edge except for
the TX_DREQ signal that is transmitted by the DME on the
falling edge and sampled by the DTIR on the rising edge. All
output signals from the DTIR to the DME are transmitted by
the DTIR on the rising edge and received by the DME on the
rising edge.
DRX-S
DRX-H
DTX-S
DTX-H
DUPLX_CLKI
DUPLX_TX
DUPLX_CLKO
DUPLX_RX
CO/RT XMT
Table III. TX Serial I/F Timing
Figure 4. Duplex Serial Port
t
DTX-S
Description
Setup Time of DUPLX_RX from
Falling Edge of DUPLX_CLKO
Hold Time of DUPLX_RX from
Falling Edge of DUPLX_CLKO
Setup Time of DUPLX_TX from
Rising Edge of DUPLX_CLKI
Hold Time of DUPLX_TX from
Rising Edge of DUPLX_CLKI
VALID DATA
DTIR XMT
DTIR RECEIVE
t
DRX-S
t
DTX-H
VALID DATA
CO/RT RECEIVE
t
DRX-H
REV. 0
Typ
5 ns
5 ns
5 ns
5 ns