ad6472 Analog Devices, Inc., ad6472 Datasheet - Page 2

no-image

ad6472

Manufacturer Part Number
ad6472
Description
2 Pair/1 Pair Etsi Compatible Hdsl Analog Front End
Manufacturer
Analog Devices, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ad6472BS
Manufacturer:
AD
Quantity:
6
Part Number:
ad6472BS
Manufacturer:
ADI
Quantity:
196
P
TRANSMIT CHANNEL
TRANSMIT DAC
TRANSMIT FILTER
LINE DRIVER
TRANSMIT VOLTAGE LEVEL
RECEIVE CHANNEL
HYBRID INTERFACE
PROGRAMMABLE GAIN AMPLIFIER
RECEIVE FILTER
TIMING RECOVERY DAC
DIGITAL INTERFACE
POWER SUPPLY VOLTAGE
POWER SUPPLY CURRENT
OPERATING TEMPERATURE RANGE
NOTES
1
Specifications subject to change without notice.
AD6472–SPECIFICATIONS
The ADC clock period t(1 f) is used for the dynamic tuning of the Tx and Rx filters.
arameter
SNR
THD
Clock Frequency
Resolution
Update Rate
Output Voltage
Corner Frequency (3 dB)
Accuracy
Gain
VCM
Output Power
Output Voltage
SNR
THD
Input Voltage Range
Input Impedance
Overall Gain Accuracy
Gain Step
Gain Step Accuracy
Corner Frequency (–3 dB)
Accuracy
Resolution
Output Low
Output High
Input Logic High, V
Input Logic L
Output Logic High, V
Output Logic Low, V
Input Logic High, V
Input Logic Low, V
Output Logic High, V
Normal Mode, Excl. Driver
OVRSAMP Mode
Line Driver
Low Power Mode
OW
, V
IL
IL
IH
IH
OL
OH
OH
1
1
Min
68
66
68
66
7
3.3
V
2.0
V
4.75
3.15
–40
DD
DD
– 0.3
– 0.3
(T
A
= T
71
12
Typ
71
2
320
535
9.53
3.53
2.5
13.5
6
6
3
71
71
10
3
320
640
0.5
4.5
5
3.3
65
73
50
17
5
1
0.25
5
MIN
to T
Max
18.688
1168
5
0.8
0.4
0.2
5.25
3.45
+85
–2–
MAX
10
10
unless otherwise noted)
dB
Bits
V
dBm
V
V
Units
dB
MHz
kHz
V p-p Diff
kHz
kHz
%
dB
dB
V p-p Diff
V p-p Diff
V p-p Diff
dB
dB
V p-p Diff
k
dB
dB
dB
kHz
kHz
%
Bits
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
C
The maximum transmit clock is 16
Condition
The complete transmit path spectrum and pulse
shape comply with ETSI requirements.
The transmit DAC maximum update rate is half
the maximum output data rate, i.e., 1168 kHz.
18.688 MHz.
MODE_SEL1 = 0
MODE_SEL1 = 1
Transformer Turns Ratio = 1:2.3 at 50 kHz
When Loaded by ETSI (RTR/TM3036)
HDSL Test Loops
TX_GAIN = 0
TX_GAIN = 1
V
Condition –6 dB to +9 dB
MODE_SEL1 = 0
MODE_SEL1 = 1
Guaranteed Monotonic
5 V Supply, V
V
5 V Supply
3.3 V Supply
V
5 V Supply, MODE_SEL1 = 0
5 V Supply, MODE_SEL1 = 1, MODE_SEL0 = 1
With 50
T
3.3 V Supply, V
CM
MIN
MIN
MIN
= 2.5 V. See Figure 3
to V
to V
to T
MAX
MAX
MAX
Differential Load
, T
MIN
MIN
MIN
to V
to V
to T
MAX
MAX
MAX
1168 =
REV. 0

Related parts for ad6472