ds3104 Maxim Integrated Products, Inc., ds3104 Datasheet - Page 27

• Manufacturer Part Number: ds3104
• Description: Ds3104 Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Figure 7-2. T0 DPLL State Transition Diagram
Rev: 012108
________________________________________________________________________________________ DS3104-SE
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
(revertive mode AND valid higher priority input)]
(revertive mode AND valid higher priority input)]
An input clock is valid when it has no activity alarm and no phase-lock alarm (see the
All input clocks are continuously monitored for activity.
Only the selected reference is monitored for loss-of-lock.
Phase lock is declared internally when the DPLL has maintained phase lock continuously for approximately 1 to 2 seconds.
To simply the diagram, the phase-lock timeout period is always shown as 100s, which is the default value of the
register. Longer or shorter timeout periods can be specified as needed by writing the appropriate value to the
When selected reference is invalid and the DPLL is not in free-run or holdover, the DPLL is in a temporary holdover state.
AND valid input clock available
[selected reference invalid OR
wait for ≤ 100s
AND valid input clock available
[selected reference invalid OR
Prelocked 2
(revertive mode AND valid higher priority input)]
out of lock >100s OR
(101)
(revertive mode AND valid higher priority input)
AND valid input clock available
[selected reference invalid OR
phase-locked
to selected
reference > 2s
[selected reference invalid OR
OR out of lock >100s] AND
valid input clock available
out of lock >100s OR
(selected reference invalid > 2s
AND no valid input clock
OR out of lock >100s)
Reset
on selected reference
phase-lock regained
within 100s
(selected reference invalid > 2s
no valid input clock available
OR out of lock >100s) AND
all input clocks evaluated
at least one input valid
wait for ≤ 100s
wait for ≤ 100s
Loss-of-Lock
Prelocked
Free-Run
select ref
Locked
(001)
(110)
(100)
(111)
phase-locked to
selected reference > 2s
loss-of-lock on
selected reference
all input clocks evaluated
at least one input valid
(selected reference invalid > 2s
no valid input clock available
OR out of lock >100s) AND
VALSR
selected reference invalid > 2s
no valid input clock available
registers and the
AND
Holdover
select ref
(010)
PHLKTO
ISR
PHLKTO
registers).
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register.