SST-SALEM-3T Analog Devices, Inc., SST-SALEM-3T Datasheet - Page 4

• Manufacturer Part Number: SST-SALEM-3T
• Description: Salem Three-phase Electronic Energy Meter
• Manufacturer: Analog Devices, Inc.

ADSST-EM-3035
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Pin
Name(s)
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2+PF7
IRQL0+PF5 1
IRQL1+PF6
IRQE+PF4
PF3
PF2 (Mode C) 1
PF1 (Mode B) 1
SPORT0 has a multichannel interface to selectively receive and
transmit a 24- or 32-word, time-division multiplexed, serial
bitstream.
SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
Number Input/
of Pins
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Output Function
I
I
O
O
O
O
O
O
O
O
O
I
I
I
I
I/O
I
I
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory
Select Output
Memory Read Enable Output
Memory Read Enable Output
Edge- or Level-Sensitive
Interrupt Request
Level-Sensitive
Interrupt Requests
Level-Sensitive
Interrupt
Edge-Sensitive
Interrupt Requests
Programmable I/O Pin
Programmable I/O Pin Mode
Select Input-Checked only
During RESET
Mode Select Input-Checked
only During RESET
Requests
1
1
1
Table I. Common-Mode Pins
1
–4–
Pin Descriptions
The ADSST-2185KST-133 is available in a 100-lead TQFP
package. To maintain maximum functionality and reduce pack-
age size and pin count, some serial ports, programmable flags,
interrupt and external bus pins have dual, multiplexed function-
ality. The external bus pins are configured during RESET only,
while serial port pins are software configurable during program
execution. Flag and interrupt functionality is retained concur-
rently on multiplexed pins. In cases where pin functionality is
reconfigurable, the default state is shown in plain text; alternate
functionality is shown in italics.
Pin
Name(s)
PF0 (Mode A) 1
CLKIN,
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1:0
F1, F0
PWD
PWDACK
FL0, FL1,
FL2
VDD
AND
GND
EX-Port
NOTES
1
2
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable
the corresponding interrupts, the DSP will vector to the appropriate interrupt
vector address when the pin is asserted, either by external devices or set as a
programmable flag.
SPORT configuration determined by the DSP System Control Register. Software
configurable.
Number Input/
of Pins
2
1
5
5
1
1
3
16
9
Output Function
I
I
O
I/O
I/O
I
O
O
I
I/O
Mode Select Input-Checked
only During RESET
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive
Interrupts
Flag In, Flag Out
Power-Down Control Input
Power-Down Control Output
Output Flags
VDD and GND
For Emulation Use
2
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