S25FL008K Meet Spansion Inc., S25FL008K Datasheet - Page 20

• Manufacturer Part Number: S25FL008K
• Description: 8-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

20
6.2.3
6.2.4
Write Disable (04h)
Read Status Register-1 (05h) and Read Status Register-2 (35h)
Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction.
Write Enable for Volatile Status Register instruction
it is only valid for the Write Status Register instruction to change the volatile Status Register bit values.
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to a 0.
The Write Disable instruction is entered by driving CS# low, shifting the instruction code “04h” into the SI pin
and then driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon completion
of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector
Erase, Block Erase and Chip Erase instructions.
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered
by driving CS# low and shifting the instruction code “05h” for Status Register-1 or “35h” for Status Register-2
into the SI pin on the rising edge of CLK. The status register bits are then shifted out on the SO pin at the
falling edge of CLK with most significant bit (MSB) first as shown in
shown in
LB3-1, CMP and SUS bits (see
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is
CS#
CLK
CS#
CLK
SO
SO
SI
SI
Figure 6.1
Figure 6.4 Write Enable for Volatile Status Register Instruction Sequence Diagram
Mode 3
Mode 0
Mode 3
Mode 0
and
D a t a
Figure 6.2
Figure 6.5 Write Disable Instruction Sequence Diagram
Section 6.1, Status Register on page
S h e e t
and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0, SRP1, QE,
0
0
S25FL008K
1
1
Instruction (50h)
2
High Impedance
Instruction (04h)
( A d v a n c e
High Impedance
2
3
(Figure
3
4
4
5
6.4) will not set the Write Enable Latch (WEL) bit,
6
5
I n f o r m a t i o n )
7
Figure
6
13).
7
6.6. The Status Register bits are
S25FL008K_00_01 July 30, 2010
Mode 0
Mode 3
Mode 0
Mode 3