S25FL032A Meet Spansion Inc., S25FL032A Datasheet - Page 21

• Manufacturer Part Number: S25FL032A
• Description: 32 Megabit Cmos 3.0 Volt Flash Memory With 50 Mhz Spi Bus Interface
• Manufacturer: Meet Spansion Inc.

9.7
July 2, 2007 S25FL032A_00_C2
Write Status Register (WRSR)
on page
Protected mode is enabled, BP2:BP0 cannot be changed. The Bulk Erase (BE) command is executed only if
all Block Protect (BP2, BP1, BP0) bits are 0.
Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write
Protect (W#) signal. When SRWD is set to 1 and W# is driven low, the device enters the Hardware Protected
mode. The non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the
device ignores any Write Status Register (WRSR) command.
The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable
(WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, is required prior to
writing the WRSR command.
bits and their functions.
The host system must drive CS# low, write the WRSR command, and the appropriate data byte on SI
(Figure
The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must
be used for that purpose. Bit 0 is a status bit controlled internally by the Flash device. Bits 6 and 5 are always
read as 0 and have no user significance.
The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit
and W# together place the device in the Hardware Protected Mode (HPM). The device ignores all WRSR
commands once it enters the Hardware Protected Mode (HPM).
and the SRWD bit must be 1 for this to occur.
Note
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 9.3
either by setting the SRWD bit after driving W# low, or by driving W# low after setting the SRWD bit.
However, the device disables HPM only when W# is driven high.
Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in
HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no
protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM).
Signal
W#
1
1
0
0
9.7).
12) is protected against Page Program (PP) and Sector Erase (SE) commands. If the Hardware
SRWD
shows that neither W# or SRWD bit by themselves can enable HPM. The device can enter HPM
Bit
1
0
0
1
Software
Protected
(SPM)
Hardware
Protected
(HPM)
Mode
Figure 9.7 Write Status Register (WRSR) Command Sequence
CS#
SCK
D a t a
SI
SO
Status Register is writable (if the WREN
command has set the WEL bit). The values in
the SRWD, BP2, BP1 and BP0 bits can be
changed.
Status Register is Hardware write protected.
The values in the SRWD, BP2, BP1 and BP0
bits cannot be changed.
Mode 3
Mode 0
Hi-Z
Table 9.2, S25FL032A Status Register on page 20
Write Protection of the Status Register
S h e e t
0
S25FL032A
1
Table 9.3 Protection Modes
2
Command
3
4
5
6
7
MSB
7
8 9 10 11 12 13 14 15
6
Status Register In
5
Table 9.3
4
3
program and erase
program and erase
Protected against
Protected against
Protected Area
2
(See Note)
commands
commands
1
shows that W# must be driven low
0
Table 7.1 on page
shows the status register
Ready to accept Page
Ready to accept Page
Program and Sector
Program and Sector
Unprotected Area
Erase commands
Erase commands
(See Note)
12.
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