EMD12324PV Emlsi Inc., EMD12324PV Datasheet - Page 13

• Manufacturer Part Number: EMD12324PV
• Description: 512m 16m X 32 Mobile Ddr Sdram
• Manufacturer: Emlsi Inc.

Functional Description
The 512Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912-
bits. It is internally configured as a quad-bank DRAM. Each of the 134,217,728-bit banks is organized as 8,192 rows by
512 columns by 32 bits.
The 512Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words
per clock cycle at the I/O balls. single read or write access for the 512Mb Mobile DDR SDRAM consists of a single 2n-
bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-
cycle data transfers at the I/O balls.
Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12
select the row). The address bits registered coincident with the READ or WRITE command are used to select the start-
ing column location for the burst access.
It should be noted that the DLL signal that is typically used on standard DDR devices is not necessary on the Mobile
DDR SDRAM. It has been omitted to save power. Prior to normal operation, the Mobile DDR SDRAM must be initial-
ized. The following sections provide detailed information covering device initialization, register definition, command
descriptions and device operation.
Initialization
Mobile DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation. If there is an interruption to the device power, the initialization rou-
tine should be followed to ensure proper functionality of the Mobile DDR SDRAM. The clock stop feature is not avail-
able until the device has been properly initialized.
To properly initialize the Mobile DDR SDRAM, this sequence must be followed:
1. To prevent device latch-up, it is recommended the core power (VDD) and I/O power (VDDQ) be from the same
2. Once power supply voltages are stable and the CKE has been driven HIGH, it is safe to apply the clock.
3. Once the clock is stable, a 200µs (minimum) delay is required by the Mobile DDR SDRAM prior to applying an exe
4. Issue a PRECHARGE ALL command.
5. Issue NOP or DESELECT commands for at least tRP time.
6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. Issue a
7. Using the LOAD MODE REGISTER command, load the standard mode register as desired.
8. Issue NOP or DESELECT commands for at least tMRD time.
9. Using the LOAD MODE REGISTER command, load the extended mode register to the desired operating modes.
10. Issue NOP or DESELECT commands for at least tMRD time.
11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command.
power source and brought up simultaneously. If separate power sources are used, VDD must lead VDDQ.
cutable command. During this time, NOP or DESELECT commands must be issued on the command bus.
second AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. As part of
the initialization sequence, two AUTO REFRESH commands must be issued. Typically, both of these com
mands are issued at this stage as described above. Alternately, the second AUTO-REFRESH command and NOP
or DESELECT sequence can be issued between steps 10 and 11.
Note that the sequence in which the standard and extended mode registers are programmed is not critical.
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512M: 16M x 32 Mobile DDR SDRAM
EMD12324PV
Preliminary
Rev 0.0