NJU26126 New Japan Radio Co.,Ltd, NJU26126 Datasheet
NJU26126
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NJU26126 Summary of contents
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... General Description The NJU26126 is a high performance 24-bit digital signal processor. The NJU26126 provides L/R channel independent 10bands PEQ, Low/High bandwidth independent DRC of FIR filter adoption, Tone Control, Lip sync Audio Delay, eala & eala Rebirth of NJRC Original Sound Enhancement, Dynamic Bass Boost, two systems Limiter, and 5 ...
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... Delay処理位置は、 The Delay processing position can be exclusively Input/SDO0/SDO1/SDO2のいずれかから排他的に選択可能です。 Selected from either of Input/SDO0/SDO1/SDO2. Fig. 2 NJU26126 Function Diagram SERIAL AUDIO INTERFACE GPIO ...
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... No.18pin do not connect or connect with V VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR capacitor of 4.7uF and 0.01uF in parallel between VSS (No.11) pin. A built-in power supply is used only for NJU26126 operation. Be not short-circuited of this pin. Do not take out the current, and connect other power supplies. ...
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... Input, I/O (Input part 22, 23pin) (with R : 18pin , With PAD Output Disable Output, I/O (Output part) ( 16, 17, 19, 20, 21pin ) ( Open Drain Output with R ( Open Drain Output: 22pin ) Fig.4 NJU26126 Terminal equivalent circuit diagram - 4 - Symbol Rating V -0 -0.3 to 2.3 REGO V -0.3 to 5.5 (V x(IN) -0 ...
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... -1mA 1mA IN(PU IN(PD) f OSC *6 CLK, MCK f JIT(CC spec. NJU26126 needs clock frequency 12.288MHz when sampling rate is 48kHz. NJU26126 ( V =3.3V, f =12.288MHz, Ta= OSC Min. Typ. Max. 3.0 3 0.8 ...
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... When SLAVEb pin is fixed on Low level, NJU26126 supplies the system clock from MCK pin. Fix the clock input pin not used to Low level because either the CLK pin or the MCK pin is supplied in NJU26126. The frequency divider for Master mode matched to the clock 256 times installed in NJU26126. ...
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... Don’t stop the supply of a clock while operating. NJU26126 installs PLL circuit internally. If the supply of a clock is stopped, PLL circuit cannot be sent a clock to the inside and NJU26126 does not operate normally. If supply of a clock is stopped or the NJU26126 is reset again, putting a normal clock into CLK terminal, the period RESETb terminal of t from initial setting ...
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... SLAVEb=”H” Firmware: Master DSP Master operating In NJU26126 is used by 256 times of Maximum sampling frequency, NJU26126 is able to output LR clock of same sampling rate and two-third times of sampling rate, and output BCK clock of 32 times sampling rate and 64 times sampling rate in Master mode. ...
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... Input terminal: Clock is generated by MCK or CLK Buffer output of CLK Multiple Frequency 32kHz 1fs 32kHz 32fs 1.024MHz 64fs 2.048MHz Buffer output of CLK NJU26126 44.1kHz 48kHz 44.1kHz 48kHz 1.4112MHz 1.536MHz 2.822MHz 3.072MHz 12.288MHz CLK pin frequency 44.1kHz 48kHz - 48kHz - 1 ...
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... This serial data format is applied to both MASTER and SLAVE mode. 3.2 Serial Audio Data Input/output The NJU26126 audio interface includes 3 data input lines: SDI0, SDI1 and SDI2 (Table 8). 3 data output lines: SDO0, SDO1 and SDO2. (Table 9). Table 8 Serial Audio Input Pin Description Pin No ...
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... The NJU26126 can use three kinds of formats hereafter as industry-standard digital audio data format; ( (2) Left-Justified (3) Right-justified and 24bits data length. (Fig.6-1 to Fig6-12) An audio interface input and output data format become the same data format. LRI, LRO BCKI, BCKO M SB ...
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... NJU26126 LRI, LRO BC KI LRI, LRO BCKI, BCKO SDI, SDO LRI, LRO BC KI Fig.6-9 Right-Justified Data Format 64fs, 18bit Data ...
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... SIL t SIH t SLI t LSI SIH t t SIL SLI Fig.7 Serial Audio Input Timing Test Condition t SLO C =25pF L t DOD t DOD Fig.8 Serial Audio Input Timing NJU26126 ( V =3.3V, Ta= Min Typ. Max Units - - 6.5 MHz ...
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... Note : SDA pin (No.22 bi-directional open drain terminal. This pin requires a pull-up resister. AD1 (No.16) pin is input pin with pull-down. AD1 (No.16) pin is connected with V resistance. When NJU26126 is stopped by power supply VDD, SDA pin and SCL pin become Hi-Z. But these pins are not 5V tolerant when VDD stops. ■ ...
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... SCL t 0.6 HD:STA t 1.3 LOW t 0.6 HIGH t 0.6 SU:STA t 0 HD:DAT t 250 SU:DAT 0.6 SU:STO t 1.3 BUF HD:DAT HIGH SU:DAT 2 Fig bus Timing NJU26126 =3.3V, f =12.288MHz, Ta= OSC Max Units 400 KHz - 0 1000 Ns 300 HD:STA t t SU:STA SU:STO ...
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... NJU26126 operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26126. When the WDC clock pulse is lost or not normal clock cycle, the NJU26126 does not operate correctly. Then reset the NJU26126 and set up the NJU26126 again. ...
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... NJU26126 Command Table Table 16 NJU26126 Command No. Command 1 Set Task 2 Fs Select 3 Smooth Control setup 4 Input Select 5 SDO0 output source select 6 SDO1 output source select 7 SDO2 output source select 8 DRC mode select 9 DRC Xover frequency select 10 Delay setup 11 System Status Configuration ...
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... NJU26126 ■ Package SSOP24-C2, Pb-Free - 18 - [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights ...