cs4244-enzr Cirrus Logic, Inc., cs4244-enzr Datasheet - Page 50

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cs4244-enzr

Manufacturer Part Number
cs4244-enzr
Description
4 In/4 Out Audio Codec With Pcm And Tdm Interfaces
Manufacturer
Cirrus Logic, Inc.
Datasheet
DS900PP2
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.2
INV SCLK
SDOUTx SW[1:0]
7
7
Sample Width Select (Address 07h)
Serial Port Control (Address 08h)
Output Sample Width
These bits set the width of the samples placed into the outgoing SDOUTx streams.
Note:
SDOUTx data stream.
Input Sample Width
These bits set the width of the samples coming into the CS4244 through the SDINx TDM streams.
Note:
Invert SCLK
When set, this bit inverts the polarity of the SCLK signal.
Serial Port Format
Sets the format of both the incoming serial data signals and outgoing serial data signals.
OUTPUT SW
00
01
10
11
INPUT SW
00
01
10
11
INV SCLK
0
1
SP FORMAT
00
01
10
11
Bits which are wider than the Output Sample Width setting above will be set to zero within the
In Left Justified or I²S mode, the Input Sample Width is fixed to 24 bits.
6
6
Sample Width is:
16 bits
18 bits
20 bits
24 bits
Sample Width is:
16 bits
18 bits
20 bits
24 bits
SCLK is:
Not Inverted
Inverted
Format is:
Left Justified
I²S
TDM (Slave Mode Only)
Reserved
Reserved[2:0]
5
5
INPUT SW[1:0]
4
4
SP FORMAT[1:0]
3
3
Reserved[1:0]
2
2
SDO CHAIN
1
1
Reserved[1:0]
MASTER /
CS4244
SLAVE
0
0
50

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