cs43l41 Cirrus Logic, Inc., cs43l41 Datasheet
cs43l41
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cs43l41 Summary of contents
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... The CS43L41 accepts data at audio sample rates from 2 kHz to 100 kHz, consumes very little power and oper- ates over a wide power supply range. These features are ideal for portable DVD, portable MP3, Mini-Disc, and mobile phones ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS43L41 DS473PP1 ...
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... CONTROL PORT INTERFACE .............................................................................................. 26 7.1 SPI Mode ......................................................................................................................... Compatible Mode ...................................................................................................... 26 7.3 Memory Address Pointer (MAP) ....................................................................................... 27 8. PARAMETER DEFINITIONS .................................................................................................. 33 Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33 Dynamic Range ...................................................................................................................... 33 Interchannel Isolation ............................................................................................................. 33 Interchannel Gain Mismatch ................................................................................................... 33 Gain Error ............................................................................................................................... 33 Gain Drift ................................................................................................................................ 33 9. REFERENCES ........................................................................................................................ 33 10. PACKAGE DIMENSIONS .................................................................................................... 34 DS473PP1 Confidential Draft 9/23/99 CS43L41 3 ...
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... Figure 20. CS43L41 Format 0 (I Figure 21. CS43L41 Format 1 (I Figure 22. CS43L41 Format 2 ....................................................................................................... 31 Figure 23. CS43L41 Format 3 ....................................................................................................... 32 Figure 24. CS43L41 Format 4 ....................................................................................................... 32 Figure 25. CS43L41 Format 5 ....................................................................................................... 32 Figure 26. CS43L41 Format 6 ....................................................................................................... 33 Figure 27. De-Emphasis Curve ..................................................................................................... 33 Figure 28. ATAPI Block Diagram .................................................................................................. 33 LIST OF TABLES Table 1. Master Clock Divide Enable ............................................................................................... 16 Table 2 ...
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... T -10 A (Note 1) unweighted TBD A-Weighted TBD - A-Weighted - (Note 1) THD - - - - kHz) - CS43L41 High-Rate Mode Typ Max Min Typ - 70 - 101 - 95 100 -89 -84 - -89 -77 -72 - -74 -37 -32 - -36 -88 ...
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... Max 0.63•VA 0.7•VA 0.77•VA - 0.5• 0 100 - 100 L High-Rate Mode Typ Max Min Typ - .4535 - - - - .4998 +.08 -0. .577 - - - ±1.39/ ±0.23/Fs - +.2/-.1 - +.05/-.14 (Note 6) - +0/-.22 CS43L41 Units Vpp VDC dB ppm/° Max Unit - Fs .4621 Fs .4982 DS473PP1 ...
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... VA = 2.28V - 5.5V) A Symbol 2 2 (AGND = 0V; all voltages with respect to ground.) Symbol IND stg (AGND = 0V; all voltages with respect to ground.) Symbol VA 2.28 CS43L41 Typ Max Units - 0 TBD ...
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... VA = 2.4V - 5.5V; Inputs: Logic 0 = 0V, A Symbol Fs MCLK/LRCK = 512 MCLK/LRCK = 512 t sclkl t sclkh t sclkw t sclkw t slrd t slrs t sdlrs t sdh (Note 9) (Note 10) t sclkw t sclkr t sdlrs t sdh t sdh CS43L41 Min Typ Max 2 - 100 10 - 1000 10 - 1000 21 - 1000 21 - 1000 31 - 1000 31 - 1000 ...
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... LRCK SCLK SDATA LRCK SDATA *INTERNAL SCLK *The SCLK pulses shown are internal to the CS43L41. LRCK MCLK *INTERNAL SCLK SDATA * The SCLK pulses shown are internal to the CS43L41. DS473PP1 t slrs t slrd t t sdlrs Figure 1. External Serial Mode Input Timing t sclkr t t sdlrs sdh Figure 2 ...
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... SCL 10 Symbol f scl t irs t buf t hdst t low t high t sust (Note 11) t hdd t sud t t susp Repeated t high t hdst sud low hdd 2 Figure Control Port Timing CS43L41 = 30 pF) L Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 300 f 4.7 - Stop Start susp ...
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... Figure 5. SPI Control Port Timing CS43L41 = 30 pF) L Min Max - 6 500 - 500 - 1 100 - 100 = 0 at all other times. spi ...
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... VA 3.3 µF 560 15 AOUTA + 10 k CS4341 MUTEC 16 9 FILT 0.1 µF .1 µF 1 µ REF_GND 3.3 µF 560 12 AOUTB + 10 k AGND 13 Figure 6. Typical Connection Diagram CS43L41 Audio Output OPTIONAL MUTE CIRCUIT + 1 µF Audio Output 560 Fs(R 560) L DS473PP1 ...
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... Default =’1’ Disabled 1 - Enabled DS473PP1 Reserved Reserved DIF1 DIF0 DEM1 24-bit data Internal SCLK 24-bit data Internal SCLK CS43L41 Reserved MCLKDIV Reserved DEM0 POR PDN ...
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... Mode Changes take effect immediately Changes take effect on zero crossings Changes take effect with a soft ramp (default) Changes take effect in 1/8 dB steps on each zero crossing VOL5 VOL4 VOL3 CS43L41 ATAPI2 ATAPI1 ATAPI0 VOL2 VOL1 VOL0 ...
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... Mute Control pin will go active during the mute period. The muting function is effected, similar to volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. AMUTE 0 Disabled 1 Enabled Table 2. Auto-Mute Enable DS473PP1 Reserved Reserved MODE DIF1 DIF0 DEM1 MODE CS43L41 Reserved MCLKDIV Reserved DEM0 POR PDN 15 ...
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... Left Justified 24-bit data Right Justified, 24-bit Data Right Justified, 20-bit Data Right Justified, 16-bit Data Right Justified, 18-bit Data Identical to Format 1 Table 3. Digital Interface Formats DIF1 DIF0 DEM1 DESCRIPTION CS43L41 DEM0 POR PDN FORMAT FIGURE ...
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... The contents of the control registers are retained in this mode. PDN 0 Disabled 1 Enabled Table 6. Power Down Enable DS473PP1 DIF1 DIF0 DEM1 MODE DIF1 DIF0 DEM1 MODE CS43L41 DEM0 POR PDN DEM0 POR PDN 17 ...
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... The zero cross function is independently mon- itored and implemented for each channel ATAPI4 ATAPI3 MODE ATAPI4 ATAPI3 CS43L41 ATAPI2 ATAPI1 ATAPI0 ATAPI2 ATAPI1 ATAPI0 DS473PP1 ...
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... Soft Zero Cross Access and write only in SPI. Default: 01001 - AOUTA=aL, AOUTB=bR (Stereo) Function: The CS43L41 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 9 and Figure 28 for additional information. ATAPI4 ATAPI3 ATAPI2 ATAPI1 ...
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... Table 10. Mute Enable 20 ATAPI0 AOUTA 1 0 MUTE 1 1 MUTE [(aL+bR)/ [(aL+bR)/ [(bL+aR)/ [(aL+bR)/ VOL5 VOL4 VOL3 MODE CS43L41 AOUTB bL [(aL+bR)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/ VOL2 VOL1 VOL0 DS473PP1 ...
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... Mute bit. Binary Code Decimal Value 0000000 0010100 0101000 0111100 1011010 Table 11. Digital Volume Settings DS473PP1 VOL5 VOL4 VOL3 Volume Setting - - - -90 dB CS43L41 VOL2 VOL1 VOL0 21 ...
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... MCLK 5 12 SCL/CCLK 6 11 SDA/CDIN 7 10 AD0/ and any current drawn from this pin will alter device perfor- CS43L41 MUTEC Mute Control AOUTA Analog Output A VA Analog Power AGND Analog Ground AOUTB Analog Output B REF_GND Reference Ground VQ Quiescent Voltage FILT+ Positive Voltage Reference is not intended to supply external current ...
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... HRM 256x* 384x* 256x 8.1920 12.2880 8.1920 11.2896 16.9344 11.2896 12.2880 18.4320 12.2880 16.3840 24.5760 - 22.5792 33.8688 - 24.5760 36.8640 - Table 12. Common Clock Frequencies CS43L41 BRM 384x 512x 768x* 12.2880 16.3840 24.5760 16.9344 22.5792 32.7680 18.4320 24.5760 36.8640 - - - - - - - - - 1024x* 32 ...
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... LRCK. External Serial Clock Mode The CS43L41 will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK. ...
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... Section 6.4 for total power-up timing. DS473PP1 6.4 Use of the Power ON/OFF Quiescent Voltage Ramp The CS43L41 uses a novel technique to minimize the effects of output transients during power-up and power-down. This technique, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients com- monly produced by single-ended single-supply converters ...
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... VA or AGND as required. The upper 6 bits of the 7-bit address field must be 001000. To communi- cate with the CS43L41 the LSB of the chip address field, which is the first byte sent to the CS43L41, should match the setting of the AD0 pin. The eighth 2 C compat- bit of the address byte is the R/W bit (high for a read, low for a write) ...
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... MAP = Memory Address Pointer Figure 7. SPI Mode Control Port Formatting Note 1 ADDR DATA R/W ACK ACK AD0 1-8 2 Figure Mode Control Port Formatting CS43L41 2 1 MAP2 MAP1 0 0 DATA LSB byte n DATA ...
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... Figure 9. Base-Rate Stopband Rejection Figure 11. Base-Rate Transition Band (Detail) Figure 13. High-Rate Stopband Rejection 28 CS43L41 Figure 10. Base-Rate Transition Band Figure 12. Base-Rate Passband Ripple Figure 14. High-Rate Transition Band DS473PP1 ...
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... Safe Operating 50 Region 25 2 Resistive Load -- R Figure 18. Maximum Loading DS473PP1 Figure 16. High-Rate Passband Ripple 3.3 µF + AOUTx R L Figure 17. Output Test Load Figure 19. Power vs. Sample Rate (VA = 5V) CS43L41 V out Sample Rate (kHz) 100 29 ...
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... LSB MSB - 24-Bit DataData Valid on Rising Edge 24-Bit data SCLK Figure 20. CS43L41 Format LSB MSB - 24-Bit DataData Valid on Rising Edge 24-Bit data SCLK Figure 21. CS43L41 Format 1 (I ...
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... Period Figure 24. CS43L41 Format Right Justified, 16-Bit DataData Valid on Rising Edge of SCLKSCLK Must Have at Least 32 Cycles per LRCK Period Figure 25. CS43L41 Format 5 CS43L41 Right Channel External SCLK Mode Right Channel ...
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... Left Channel Audio Data Right Channel Audio Data Right Justified, 18-Bit DataData Valid on Rising Edge of SCLKSCLK Must Have at Least 36 Cycles per LRCK Period Figure 26. CS43L41 Format 6 Gain dB T1=50 µs 0dB -10dB F1 F2 3.183 kHz 10.61 kHz Figure 27. De-Emphasis Curve ...
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... Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters” by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB43L41 Evaluation Board Datasheet 2 3) “The I C Bus Specification: Version 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com DS473PP1 CS43L41 33 ...
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... SEATING PLANE SIDE VIEW INCHES MIN MAX -- 0.043 0.002 0.006 0.034 0.037 0.008 0.012 0.193 0.201 0.248 0.256 0.169 0.177 -- 0.026 0.020 0.028 0° 8° CS43L41 1 E1 END VIEW L MILLIMETERS NOTE MIN MAX -- 1.10 0.05 0.15 0.85 0.95 0.19 0.30 2,3 4.90 5.10 1 6.30 6.50 4.30 4. 0.65 0.50 0.70 0° 8° DS473PP1 ...
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Notes • ...
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