cs4412 Cirrus Logic, Inc., cs4412 Datasheet - Page 13

• Manufacturer Part Number: cs4412
• Description: 30 W Quad Half-bridge Digital Amplifier Power Stage Logic
• Manufacturer: Cirrus Logic, Inc.

DS749A1
4. APPLICATIONS
4.1
4.2
4.2.1
4.2.2
Overview
The CS4412 is a high-efficiency power stage for digital Class-D amplifiers designed to be configured as four
half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge channels, or one
parallel full-bridge channel.
The CS4412 integrates on-chip over-current, under-voltage, over-temperature protection and error report-
ing as well as a thermal warning indicator. The low R
delivering
ments, and smaller power supplies.
Reset and Power-Up
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks, and
configuration pins are stable. It is also recommended that the RSTx/y pin be activated if the voltage supplies
drop below the recommended operating condition to prevent power-glitch- related issues.
When RSTx/y is low, the corresponding channels of the CS4412 enter a low-power mode and all of the
channels’ internal states are reset and the outputs are set to HI-Z. When RSTx/y is high, the desired mode
settings will be loaded and the outputs will begin normal operation.
PWM Popguard Transient Control
The CS4412 uses Popguard technology to minimize the effects of output transients during power-up and
power-down for half-bridge configurations. This technique reduces the audio transients commonly pro-
duced by half-bridge, single-supply amplifiers when implemented with external DC-blocking capacitors
connected in series with the audio outputs.
When the device is configured for ramping (RAMP set high) and RSTx/y is set high, the OUTx/y outputs
will ramp-up to the bias point (VP/2). This gradual voltage ramping allows time for the external DC-block-
ing capacitor to charge to the quiescent voltage, minimizing the power-up transient. The OUTx/y outputs
will not begin normal operation until the ramp has reached the bias point. The INx/y inputs must begin
switching before the ramp cycle begins.
When the device is configured for ramping (RAMP set high) and RSTx/y is set low, the OUTx/y outputs
will begin to slowly ramp down from the bias point to PGND, allowing the DC-blocking capacitor to dis-
charge.
The ramp feature should only be used in quad half-bridge configuration. It is not necessary to complete a
ramp-up/down sequence before ramping up/down again.
Recommended Power-Up Sequence
1. Turn on the system power.
2. Hold RSTx/y low until the power supply and system clocks are stable. In this state, all associated
3. Start the PWM modulator output.
4. Once the PWM modulator output is valid, release RSTx/y high. If the CS4412 is configured for
outputs are HI-Z.
ramping, the outputs will ramp to the bias point and then begin switching normally. If the CS4412 is
not configured for ramping, the outputs will immediately begin switching normally.
85%
efficiency. This efficiency provides for smaller device package, no external heat sink require-
DS(ON)
outputs can source up to
2.4 A
peak current,
CS4412
13