cs840002agi-0i1 Integrated Device Technology, cs840002agi-0i1 Datasheet

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cs840002agi-0i1

Manufacturer Part Number
cs840002agi-0i1
Description
Femtoclocks?? Crystal-to Lvcmos/lvttl Frequency Synthesizer
Manufacturer
Integrated Device Technology
Datasheet
1.CS840002AGI-0I1.pdf (13 pages)
www.IDT.com
G
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
156.25MHz, 125MHz, and 62.5MHz. The ICS840002I-01 uses
IDT’s 3
can achieve 1ps or lower typical random rms phase jitter,
easily meeting Ethernet jitter requirements. The ICS840002I-
01 is packaged in a small 16-pin TSSOP package.
F
B
840002AGI-01
nXTAL_SEL
XTAL_OUT
TEST_CLK
HiPerClockS™
nPLL_SEL
REQUENCY
F
IC S
F_SEL1:0
LOCK
XTAL_IN
_
ENERAL
S
0
0
1
1
E
L
MR
rd
OE
1
generation low phase noise VCO technology and
Pullup
Pullup:Pullup
Pulldown
Pulldown
Pulldown
Pulldown
F
S
D
the HiPerClocks
clock solutions from IDT. Using a 25MHz 18pF
25MHz
The ICS840002I-01 is a 2 output LVCMOS/LVTTL
Synthesizer optimized to generate Ethernet
reference clock frequencies and is a member of
_
ELECT
S
OSC
IAGRAM
0
0
1
1
E
D
L
0
ESCRIPTION
F
UNCTION
M
0
1
D
n I
v i
p
d i
TM
u
2
2
2
2
Detector
r e
5
5
5
5
T
s t
Phase
ABLE
family of high performance
V
a
u l
e
2
M = ÷25 (fixed)
N
D
v i
VCO
d i
1
4
5
5
r e
0
V
a
u l
e
1
0
O
u
1
LVCMOS/LVTTL F
2 (
p t
F
• Two LVCMOS/LVTTL outputs @ 3.3V,
• Selectable crystal oscillator interface
• Supports the following output frequencies:
• Output frequency range: 56MHz - 175MHz
• VCO range: 560MHz - 700MHz
• Output skew: 12ps (maximum)
• RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
• Power supply modes:
• -40°C to 85°C ambient operating temperature
5
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1 ÷5
t u
17
or LVCMOS single-ended input
156.25MHz, 125MHz and 62.5MHz
0.47ps (typical)
100kHz ............. -126.1 dBc/Hz
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
Available in both standard (RoHS 5) and lead-free RoHS
(6) packages
M
EATURES
1
F_SEL1:0
Offset
100Hz ............... -97.4 dBc/Hz
10kHz ............. -127.6 dBc/Hz
5
6
1
1
F
H
1kHz ............. -120.2 dBc/Hz
2
6
2
2
N
e r
z
2 .
5 .
5
5
typical output impedance
q
R
5
u
e
e
) . f
n
c
y
F
EMTO
Noise Power
Q0
Q1
ICS840002I-01
REQUENCY
C
P
nXTAL_SEL
TEST_CLK
4.4mm x 5.0mm x 0.92mm
nPLL_SEL
LOCKS
IN
F_SEL0
A
ICS840002I-01
V
16-Lead TSSOP
V
MR
OE
DDA
DD
package body
SSIGNMENT
G Package
™ C
Top View
1
2
3
4
5
6
7
8
S
REV. A OCTOBER 22, 2007
YNTHESIZER
RYSTAL
16
15
14
13
12
11
10
9
F_SEL1
GND
GND
Q0
Q1
V
XTAL_IN
XTAL_OUT
DDO
-
TO
-

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cs840002agi-0i1 Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS840002I- output LVCMOS/LVTTL IC S Synthesizer optimized to generate Ethernet reference clock frequencies and is a member of HiPerClockS™ the HiPerClocks TM family of high performance clock solutions from IDT. Using ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG T 3A ...

Page 4

T 3C. LVCMOS/LVTTL DC C ABLE HARACTERISTICS 3.3V±5 2.5V±5 DDA DDO ...

Page 5

T 5B ABLE HARACTERISTICS ...

Page 6

T YPICAL 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k T YPICAL 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 ...

Page 7

P ARAMETER 1.65V± DDA DDO LVCMOS GND -1.65V±5% 3.3V C /3. ORE UTPUT OAD 1.25V± DDA DDO LVCMOS GND -1.25V±5% 2.5V C /2.5V ...

Page 8

OWER UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840002I-01 provides separate power supplies to isolate any high switching noise from the outputs ...

Page 9

L G AYOUT UIDELINE Figure 3 shows a schematic example of the ICS840002I-01. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an ...

Page 10

ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row ...

Page 11

ACKAGE UTLINE UFFIX FOR 840002AGI-01 LVCMOS/LVTTL F TSSOP EAD ABLE ACKAGE IMENSIONS ...

Page 12

ABLE RDERING NFORMATION ...

Page 13

840002AGI-01 LVCMOS/LVTTL ...

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