cs8952t Cirrus Logic, Inc., cs8952t Datasheet - Page 59
cs8952t
Manufacturer Part Number
cs8952t
Description
100base 10base-t Transceiver
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CS8952T.pdf
(86 pages)
- Current page: 59 of 86
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Self Status Register - Address 19h (Cont.)
DS206TPP2
5
4:0
CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
BIT
CIM Status
PHY Address Field Read/Write Reset to the val-
NAME
Read Only
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
TYPE
0
ues on the
PHYAD[4:0] pins.
RESET
When clear, this bit indicates that a stable link con-
nection has been detected. When an unstable link is
detected and the Carrier Integrity Monitor Disable bit
in the PCS Sub-Layer Configuration Register
(address 17h) is clear, this bit is set and latched. It will
remain set until this register is read.
The value on pins PHYAD[4:0] are latched into this
field at power-up or reset. These bits define the PHY
address used by the management layer to address
the PHY. The external logic must know this address
in order to select this particular CS8952T’s registers
individually via the MDIO and MDC pins.
DESCRIPTION
59
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