cs1160 Shenzhen Chipsea Technologies CO., LTD, cs1160 Datasheet - Page 15

• Manufacturer Part Number: cs1160
• Description: Analog-to-digital A/d Converter
• Manufacturer: Shenzhen Chipsea Technologies CO., LTD

3.8
The CS1160 can communicate with external controller through the SPI bus. The CS1160 only
operates in slave mode. The serial interface is a standard four-wire SPI interface, including CS, SCLK,
SDI and SDO.
3.8.1
Before communicating with the CS1160, the external controller must send the chip select (CS) signal
to the chip. During communication, the CS signal must be maintained at low. When the CS signal is
high, the entire SPI is reset. CS can be hard-wired low, the SPI bus can work in the three-wire mode
which fits for communicating with external controller.
3.8.2
The serial clock features a Schmitt-triggered input, which is used for sampling the SDI and SDO
signals. The SCLK must be very clean to prevent the sample error. If the SCLK doesn’t appear in
three DRDY cycles, the SPI bus is reset on next SCLK and starts a new communication cycle. A
special waveform can reset the entire chip. See the RESET chapter for more information.
3.8.3
The data input pin (SDI) and the data output pin (SDO) receive and send data. The SDO is high
impendence when unused, allowing SDI and SDO to be connected together and driven by a
bidirectional bus.
3.8.4
The DRDY signal is used for indicating the status of data registers. When the new data in the data
output register (DOR) is ready, the DRDY signal goes low. After a read operation, the DRDY signal
goes high. When the DOR register is ready to update, the DRDY goes high, which indicates the data
in DOR can’t be read.
The status of DRDY also can be got from the seventh bit of ACR register.
3.9
The power-on reset circuit is designed to reset the CS1160 automatically after power-up.
The CS1160 can be reset through two methods when the CS1160 is working: sending RESET
command, or sending specific waveform on the SCLK (the SCLK RESET waveform, as shown in the
Timing Diagram of the CS1160).
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SERIAL PERIPHERAL INTERFACE (SPI)
POWER-UP RESET and CHIP RESET
CHIP SELECT (CS)
SERIAL CLOCK (SCLK)
DATA INPUT (SDI) and DATA OUTPUT (SDO)
DATA READY (DRDY)
Shenzhen Chipsea Technologies CO., LTD.
CS1160 Specification
www.chipsea.com
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