cynse70032 Cypress Semiconductor Corporation., cynse70032 Datasheet - Page 20

• Manufacturer Part Number: cynse70032
• Description: Network Search Engine
• Manufacturer: Cypress Semiconductor Corporation.

The single Read operation takes six clock cycles that are performed in the following sequence.
At the termination of cycle 6, the selected device releases the ACK line to a three-state condition. The Read instruction is
complete, and a new operation can begin. Note. The latency of the SRAM Read will be different than the one described above
(see Subsection 15.2, “SRAM PIO Access” on page 99). Table 12-4 lists and describes the format of the Read address for a data
array, mask array, or SRAM.
Table 12-5 describes the Read address format for the internal registers. Figure 12-2 illustrates the timing diagram for the burst
Read of the data or mask array.
Table 12-4. Read Address Format for Data Array, Mask Array, or SRAM
Document #: 38-02042 Rev. *E
Note:
Reserved 0: Direct
Reserved 0: Direct
Reserved 0: Direct
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the DQ bus supplies
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[67:0] bus, and drives the ACK signal from Z to low.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[67:0] bus, and drives the ACK
• Cycle 6: The selected device floats the DQ[67:0] to a three-state condition and drives the ACK signal low.
6.
[67:30]
the address as shown in Table 12-4 and Table 12-5. The host ASIC selects the CYNSE70032 device for which ID[4:0] matches
the DQ[25:21] lines. If DQ[25:21] = 11111, the host ASIC selects the CYNSE70032 with the LDEV bit set. The host ASIC also
supplies SADR[21:19] on CMD[8:6] in cycle A of the Read instruction if the Read is directed to the external SRAM.
signal high.
DQ
“ | ” stands for logical OR operation. “{}” stands for concatenation operator.
1: Indirect
1: Indirect
1: Indirect
[29]
DQ
CMD[8:2]
CMD[1:0]
CLK2X
PHS_L
CMDV
ACK
(applicable if
(applicable if
(applicable if
DQ
SSR Index
SSR Index
SSR Index
DQ[29] is
DQ[29] is
DQ[29] is
indirect)
indirect)
indirect)
[28:26]
DQ
[25:21]
Figure 12-1. Single-Location Read Cycle Timing
DQ
ID
ID
ID
cycle
A
Address
1
Read
01: Mask
00: Data
External
[20:19]
SRAM
Array
Array
DQ
10:
B
cycle
2
Reserved If DQ[29] is 0, this field carries the address of the data array
Reserved If DQ[29] is 0, this field carries the address of the mask array
Reserved If DQ[29] is 0, this field carries the address of the SRAM
[18:14]
DQ
cycle
3
location. If DQ[29] is 1, the SSR Index specified on
DQ[28:26] is used to generate the address of the data array
location: {SSR[13:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
location. If DQ[29] is 1, the SSR Index specified on
DQ[28:26] is used to generate the address of the mask array
location: {SSR[13:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
location. If DQ[29] is 1, the SSR Index specified on
DQ[28:26] is used to generate the address of the SRAM
location: {SSR[13:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
cycle
4
X
cycle
5
Data
DQ[13:0]
cycle
6
CYNSE70032
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