ad5066bruz-1reel7 Analog Devices, Inc., ad5066bruz-1reel7 Datasheet - Page 16

• Manufacturer Part Number: ad5066bruz-1reel7
• Description: Fully Accurate 16-bit Unbuffered Vout Dac Spi Interface 2.7 V To 5.5 V In A Tssop
• Manufacturer: Analog Devices, Inc.

AD5066
CLEAR CODE REGISTER
The AD5066 has a hardware CLR pin that is an asynchronous
clear input. The CLR input is falling edge sensitive. Bringing the
CLR line low clears the contents of the input register and the
DAC registers to the data contained in the user-configurable
CLR register and sets the analog outputs accordingly. (see Table
13 ) This function can be used in system calibration to load zero
scale, midscale, or full scale to all channels together. These clear
code values are user-programmable by setting two bits, Bit DB1
and Bit DB0, in the control register (see Table 13 ). The default
setting clears the outputs to 0 V. Command 0101 is reserved for
loading the clear code register (see Table 7).
The part exits clear code mode on the 32
next write to the part. If CLR is activated during a write
sequence, the write is aborted.
The CLR pulse activation time—the falling edge of CLR to when
the output starts to change—is typically
outside the DAC linear region, it typically takes
executing CLR for the output to start changing (see Error!
Reference source not found. ).
See Table 14 for contents of the input shift register during the
loading clear code register operation
LDAC FUNCTION
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin.
Synchronous LDAC : After new data is read, the DAC registers
are updated on the falling edge of the 32
can be permanently low or pulsed as in Figure 3
Asynchronous LDAC : The outputs are not updated at the same
time that the input registers are written to. When LDAC goes
low, the DAC registers are updated with the contents of the
input register.
Alternatively, the outputs of all DACs can be updated
simultaneously using the software LDAC function by writing to
Input Register n and updating all DAC registers. Command
0010 is reserved for this software LDAC function.
An LDAC register gives the user extra flexibility and control
over the hardware LDAC pin. This register allows the user to
select which combination of channels to simultaneously update
when the hardware LDAC pin is executed. Setting the LDAC bit
register to 0 for a DAC channel means that this channel’s update
is controlled by the LDAC pin. If this bit is set to 1, this channel
TBD
nd
nd
SCLK pulse. LDAC
falling edge of the
ns. However, if
TBD
ns after
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updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the LDAC pin.
It effectively sees the LDAC pin as being tied low. (See Table 15
for the LDAC register mode of operation.) This flexibility is
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
Writing to the DAC using command 0110 loads the 4-bit LDAC
register (DB3 to DB0). The default for each channel is 0; that is,
the LDAC pin works normally. Setting the bits to 1 means the
DAC channel is updated regardless of the state of the LDAC
pin. See Table 16 for the contents of the input shift register
during the load LDAC register mode of operation.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5066 should
have separate analog and digital sections. If the AD5066 is in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the AD5066.
The power supply to the AD5066 should be bypassed with 10 µF
and 0.1 µF capacitors. The capacitors should physically be as
close as possible to the device, with the 0.1 µF capacitor ideally
right up against the device. The 10 µF capacitors are the
tantalum bead type. It is important that the 0.1 µF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), such as is typical of common ceramic types of
capacitors. This 0.1 µF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is
the microstrip technique, where the component side of the
board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, this is not always
possible with a 2-layer board.
Preliminary Technical Data