ir3500a International Rectifier Corp., ir3500a Datasheet - Page 30

• Manufacturer Part Number: ir3500a
• Description: Xphase3 Vr11.0 & Amd Pvid Control Ic
• Manufacturer: International Rectifier Corp.

DESIGN PROCEDURE
Oscillator Resistor Rosc
The oscillator of IR500 generates square-wave pulses to synchronize the phase ICs. The switching frequency of
each phase converter equals the PHSOUT frequency, which is set by the external resistor R
curve in Figure 23. The CLKOUT frequency equals the switching frequency multiplied by the phase number. The
Rosc sets the reference current used for the no load offset and OCSET which is given by Figure 23 and equals:
Soft Start Capacitor C
The soft start capacitor C
start time, VID sample delay time, VR ready delay time and over-current fault latch delay time after VR ready.
For the converter using VR11 VID with boot voltage, the SS/DEL pin voltage controls the slew rate of the
converter output voltage, as shown in Figure 10. After the ENABLE pin voltage rises above 0.85V, there is a soft-
start delay time TD1
soft start time TD2 represents the time during which converter voltage rises from zero to 1.1V
delay time (TD3) is the time period when VID stays at boot voltage of 1.1V. VID rise or fall time (TD4) is the time
when VID changes from boot voltage to the final voltage. The VR ready delay time (TD5) is the time period from
VR reaching the final voltage to the VR ready signal being issued, which is determined by the delay comparator
threshold.
C
For the converter using VR 11 VID without boot voltage or AMD 5-bit and 6-bit VIDs, the SS/DEL pin voltage
controls the slew rate of the converter output voltage, as shown in Figure 11. After the ENABLE pin voltage rises
above 0.85V/1.2V, there is a soft-start delay time TD1
the soft start. The soft start time TD2 represents the time during which converter voltage rises from zero to Vo
ready delay time (TD3) is the time period from VR reaching the final voltage to the VR ready signal being issued.
Calculate C
SS/DEL
Page 30 of 47
= 0.1uF meets all the specifications of TD1 to TD5, which are determined by (2) to (6) respectively.
SS/DEL
based on the required soft start time (TD2).
,
after which the error amplifier output is released to allow the soft start of output voltage. The
SS/DEL
TD
TD
TD
TD
TD
C
SS/DEL
SS
1
2
4
5
3
/
=
DEL
=
=
=
=
C
C
C
C
SS
C
SS
SS
=
programs five different time parameters. They include soft start delay time, soft
ISETPT
SS
/
SS
I
TD
I
/
/
DEL
CHG
DEL
DEL
CHG
/
/
DEL
DEL
2
V
I
1 *
*
1 *
*
CHG
O
I
( *
I
V
*
4 .
CHG
CHG
1 .
=
I
DAC
3 (
. 3
CHG
IOCSET
=
=
92
−
C
C
=
−
52
52
1
SS
SS
1
TD
−
4 .
1 .
5 .
5 .
/
/
DEL
DEL
) 3
2
*
*
−
=
=
10
10
*
1
−
C
52
1 *
. 0
1 *
V
Rosc
) 1 .
−
−
SS
TD
6
,
O
595
6
5 .
4 .
1 .
after which the error amplifier output is released to allow
/
*
=
DEL
52
4
10
C
5 .
=
−
52
*
6
SS
*
C
V
10
5 .
/
DAC
52
SS
DEL
−
*
/
6
5 .
DEL
10
−
*
*
1
0
−
1 .
10
*
6
7 .
. 0
−
6
92
(1)
−
TD
4
(6)
(4)
(5)
(2)
(3)
(7)
OSC
July 3, 2008
.
IR3500A
The VID sample
according to the
.
VR