ir3084a International Rectifier Corp., ir3084a Datasheet - Page 12

• Manufacturer Part Number: ir3084a
• Description: Xphase Tm Vr 10/11 Control Ic
• Manufacturer: International Rectifier Corp.

ENABLE
RMPOUT
VOSNS-
VBIAS
VIDSEL
SS/DEL
ROSC
LGND
IR3084A THEORY OF OPERATION
Block Diagram
VID Control
An 8 bit VID voltage compatible with VR 10 (see Table 1) and VR11 (see Table 2) is available at the VDAC pin.
The VIDSEL pin configures the DAC for VR10 if grounded or connected to VCC (12V) and for VR11 if floated or
connected to VBIAS (6.9V). The VIDSEL pin is internally pulled up to 1.25V through a 12.5Kohm resistor. The
VID pins require an external bias voltage and should not be floated. The VID input comparators, with 0.6V
threshold, monitor the VID pins and control the 8 bit Digital to Analog Converter (DAC) whose output is sent to
the VDAC buffer amplifier. The output of the buffer amp is the VDAC pin. The VDAC voltage is post-package
trimmed to compensate for the input offsets of the Error Amp to provide a 0.5% system accuracy. The actual
VDAC voltage does not represent the system set point and has a wider tolerance.
VCC
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
12.5K
850mV
750mV
9.9V
9.1V
1.25V
Page 12 of 45
+
-
+
-
IDISCHG
6.5uA
VID INPUT
COMPARATORS
(1 of 8 shown)
+
-
100k
VCC UVLO
COMPARATOR
0.6V
-
+
250ns
BLANKING
+
-
RAMP GENERATOR
ON
+
-
50%
DUTY
CYCLE
IVOSNS-
1.3mA
VCHG
3.85V
ICHG
70uA
ENABLE
COMPARATOR
-
+
IROSC
IROSC
IROSC
IROSC
IROSC
IROSC
IROSC
IROSC
IROSC
"FAST" VDAC
DIGITAL TO
ANALOG
CONVERTER
1.1V
+
-
4.8V
0.9V
100mV
80mV
1.1V
OFF
1.1V
VBIAS
IROSC
I_OC_DISCHG
40uA
OC DELAY
COMPARATOR
0.62V
Figure 7 – IR3084A Block Diagram
7.5V
3.5V
-
+
SET VR10 DAC
SET VR11 DAC
SET VID = 1.1V BOOT
0.215V
VID FAULT CODE
CURRENT
SOURCE
GENERATOR
-
+
-
+
-
+
SS DISCHARGE
COMPARATOR
SS/DEL DISCHARGE
ON
-
+
+
-
VBIAS
REGULATOR
6.9V
IROSC
ROSC
BUFFER
AMP
1.24V
ENABLE 1.1V BOOT
1.3us
BLANKING
+
-
VCC
STARTUP
IROSC
+
-
3.1V
UVLO
DISABLE
OVER CURRENT
NO CPU
VID SAMPLE
DELAY COMPARATOR
NO CPU LATCHED
IREGSET
ISOURCE
ISINK
VDAC
BUFFER
AMP
SOFTSTART
CLAMP
-
+
+
-
S
R
COMPARATOR
1.3V
OC
IOCSET
NO CPU
FAULT
LATCH
+
-
IROSC
FAULT
LATCH
S
R
FAULT
0.6V
0.35V
IROSC
SS/DEL
S
R
IR3084A
EAOUT
+
-
10/30/2006
IOFFSET
START
LATCH
-
+
-
+
+
-
+
-
+
BIAS
REGULATOR
ERROR AMP
STARTUP
DISABLE
ERROR
AMP
S
VDRP
AMP
R
IIN
PRECONDITION
LATCH
REGDRV
VSETPT
REGSET
OCSET
REGFB
VRRDY
EAOUT
VDRP
12.5K
VDAC
FB
IIN