irs20955 International Rectifier Corp., irs20955 Datasheet - Page 17

• Manufacturer Part Number: irs20955
• Description: Protected Digital Audio Driver
• Manufacturer: International Rectifier Corp.

Power Supply Decoupling
As the IRS20955S contains analog circuitry, careful
attention must be given to decoupling the power
supplies for proper operation. Ceramic capacitors of
0.1 µF or more should be placed close to the power
supply pins of the IC on the board.
Please refer to the application note AN-978 for
general design considerations of a high voltage gate
driver IC.
V
V
missing in a dual supply configuration. In this case,
excessive negative V
could damage the IRS20955S. Having a diode to
clamp
recommended to protect the IC. A standard
recovery diode with a current rating of 1 A such as
the 1N4002 is sufficient for this purpose.
Junction Temperature Estimation
The power dissipation in the IRS20955S is
dominated by the following items:
www.irf.com
SS
SS
Negative Bias Clamping
-
-
-
-
-
1. P
The power dissipation of the floating input
section is given by:
can go below COM when a negative supply is
Figure 21. Negative V
P
logic and protection circuitry
P
shifter
P
P
level shifter
P
Input Logic and Protection Circuitry
potential
MID
LSM
LOW
LSH
HIGH
MID
P
: Power dissipation of the floating input
: Power Dissipation of the Floating
: Power dissipation of the high-side
: Power dissipation of the input level
: Power dissipation in low-side
MID
: Power dissipation in high-side
Clamping Diode
Negative VSS
=
P
ZDD
negative
SS
+
voltage with respect to COM
P
LDD
VDD
CSD
VREF
OCSET
VSS
NC
DT
IN
≈
SS
V
biases
+
Clamping
BUS
CSH
VCC
COM
HO
VS
NC
LO
VB
R
DD
−
-Vbus
V
DD
to
⋅
V
DD
V
SS
is
where
P
circuitry
P
stage to LO
R
the IRS20955S
R
MOSFET driver, typically 10 Ω for the IRS20955S
R
MOSFET
Q
LDD
LO
O
g(int)
g
g
= the external gate resistance of the low side
= total gate charge of the low side MOSFET
= the output impedance of LO, typically 10 Ω for
where
P
Zener diode clamping V
P
logic circuitry
V
R
*For obtaining the value of R
section “Supplying V
2. P
P
where
f
V
COM
3. P
The power dissipation in low-side comes from
the losses of the logic circuitry and the losses of
driving LO.
= the power dissipation from the gate drive
=
P
SW
= the power dissipation from the internal logic
= the internal gate resistance of the low side
ZDD
LDD
+BUS
LSM
SS,BIAS
LOW
DD
(
I
= the PWM switching frequency
QCC
Level Shifter
= the resistor feeding V
=
= 2 nC x f
= the power dissipation from the internal
LSM
LOW
= the power dissipation from the internal
= the positive bus voltage feeding V
⋅
P
V
= the bias voltage of V
LDD
CC
: Power Dissipation of the Input
: Power Dissipation in Low-Side
)
+
+
P
⎛
⎜
⎜
⎝
LO
Vcc
sw
IRS20955(S)PbF
x V
⋅
Q
g
DD
SS,BIAS
⋅
f
.”
SW
DD
⋅
R
DD
O
+
from V
SS
R
R
DD
g
O
with respect to
+
, refer to the
R
g
+BUS
(int)
⎞
⎟
⎟
⎠
17
DD