lt1720is8-trpbf Linear Technology Corporation, lt1720is8-trpbf Datasheet - Page 16

• Manufacturer Part Number: lt1720is8-trpbf
• Description: Dual/quad, 4.5ns, Single Supply 3v/5v Comparators With Rail-to-rail Outputs
• Manufacturer: Linear Technology Corporation

LT1720/LT1721
Timing Skews
For a number of reasons, the LT1720/LT1721’s superior
timing specifications make them an excellent choice for
applications requiring accurate differential timing skew.
The comparators in a single package are inherently well
matched, with just 300ps t
struction keeps the delays well matched vs supply voltage
and temperature. Crosstalk between the comparators,
usually a disadvantage in monolithic duals and quads, has
minimal effect on the LT1720/LT1721 timing due to the
internal hysteresis, as described in the Speed Limits
section.
The circuits of Figure 11 show basic building blocks for
differential timing skews. The 2.5k resistance interacts
with the 2pF typical input capacitance to create at least
A differential and a single-ended version are shown. In the
differential configuration, the output edges can be smoothly
scrolled through t = 0 with negligible interaction.
3ns Delay Detector
It is often necessary to measure comparative timing of
pulse edges in order to determine the true synchronicity of
clock and control signals, whether in digital circuitry or in
16
APPLICATIONS
4ns delay, controlled by the potentiometer setting.
INPUT
V
REF
2.5k
U
INFORMATION
U
C
C
C
C
IN
IN
IN
IN
Figure 11. Building Blocks for Timing Skew Generation with the LT1720
PD
LT1720
+
–
–
+
typical. Monolithic con-
W
DIFFERENTIAL 4ns
RELATIVE SKEW
U
INPUT
high speed instrumentation. The circuit in Figure 12 is a
delay detector which will output a pulse when signals X
and Y are out of sync (specifically, when X is high and Y is
low). Note that the addition of an identical circuit to detect
the opposite situation (X low and Y high) allows for full
skew detection.
Comparators U1A and U1B clean up the incoming signals
and render the circuit less sensitive to input levels and
slew rates. The resistive divider network provides level
shifting for the downstream comparator’s common mode
input range, as well as offset to keep the output low except
during a decisive event. When the upstream comparator’s
outputs can overcome the resistively generated offset
(and hysteresis), comparator U1C performs a Boolean
“X*_Y” function and produces an output pulse (see Fig-
ure 13). The circuit will give full output response with
input delays down to 3ns and partial output response with
input delays down to 1.8ns. Capacitor C1 helps ensure that
an imbalance of parasitic capacitances in the layout will
not cause common mode excursions to result in differen-
tial mode signal and false outputs.
1
Make sure the input levels at X and Y are not too close to the 0.5V threshold set by the R8–R9
divider. If you are still getting false outputs, try increasing C1 to 10pF or more. You can also look
for the problem in the impedance balance (R5 || R6 = R7) at the inputs of U1C. Increasing the offset
by lowering R5 will help reject false outputs, but R7 should also be lowered to maintain impedance
balance. For ease of design and parasitic matching, R7 can be replaced by two parallel resistors
equal to R5 and R6.
V
REF
2.5k
C
C
C
C
IN
IN
IN
IN
LT1720
+
–
–
+
1
1720/21 F11
0ns TO 4ns
SINGLE-ENDED
DELAY
17201fa