lt1719cs8-trpbf Linear Technology Corporation, lt1719cs8-trpbf Datasheet - Page 8

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lt1719cs8-trpbf

Manufacturer Part Number
lt1719cs8-trpbf
Description
4.5ns Single/dual Supply 3v/5v Comparator With Rail-to-rail Output
Manufacturer
Linear Technology Corporation
Datasheet
LT1719
APPLICATIONS
Power Supply Configurations (SO-8 Package)
The LT1719S8 has separate supply pins for the input and
output stages that allow flexible operation, accommodat-
ing separate voltage ranges for the analog input and the
output logic. Of course, a single 3V/5V supply may be used
by tying + V
The minimum voltage requirement can be simply stated as
both the output and the input stages need at least 2.7V and
the V
The following rules must be adhered to in any
configuration:
Although the ground pin need not be tied to system
ground, most applications will use it that way. Figure 1
shows three common configurations. The final one is
uncommon, but it will work and may be useful as a level
translator; the input stage is run from – 5.2V and ground
while the output stage is run from 3V and ground. In this
case the common mode input voltage range does not
include ground, so it may be helpful to tie V
anyway. Conversely, V
as long as the above rules are not violated.
Input Voltage Considerations
The LT1719 is specified for a common mode range of
–100mV to 3.8V when used with a single 5V supply. A
more general consideration is that the common mode
range is 100mV below V
criterion for this common mode limit is that the output still
responds correctly to a small differential input signal. If
one input is within the common mode limit, the other input
signal can go outside the common mode limits, up to the
absolute maximum limits, and the output will retain the
correct polarity.
When either input signal falls below the negative common
mode limit, the internal PN diode formed with the sub-
strate can turn on, resulting in significant current flow
through the die. An external Schottky clamp diode
8
2.7V (V
2.7V (+ V
(+ V
V
EE
EE
S
pin must be equal to or less than ground.
– V
Ground
S
CC
EE
and V
S
) 10.5V
– V
– GND) 6V
CC
U
EE
) 10.5V
together as well as GND and V
CC
EE
INFORMATION
may also be tied below ground,
U
/V
to 1.2V below V
W
CC
U
CC
/V
+
to 3V
. The
EE
.
between the input and the negative rail can speed up
recovery from negative overdrive by preventing the sub-
strate diode from turning on.
When both input signals are below the negative common
mode limit, phase reversal protection circuitry prevents
false output inversion to at least – 400mV common mode.
However, the offset and hysteresis in this mode will
increase dramatically, to as much as 15mV each. The input
bias currents will also increase.
When both input signals are above the positive common
mode limit, the input stage will get debiased and the output
polarity will be random. However, the internal hysteresis
will hold the output to a valid logic level. When at least one
of the inputs returns to within the common mode limits,
recovery from this state can take as long as 1 s.
The propagation delay does not increase significantly
when driven with large differential voltages, but with low
levels of overdrive, an apparent increase may be seen with
large source resistances due to an RC delay caused by the
2pF typical input capacitance.
Input Protection
The input stage is protected against damage from large
differential signals, up to and beyond a differential voltage
Figure 1. Variety of SO-8 Power Supply Configurations
Single Supply
10V
+
10V
+
LT1719S8
LT1719S8
2.7V TO 6V
V
V
V
V
IN
CC
EE
CC
EE
, 5V
5V
OUT
GND
+ V
GND
+ V
S
S
Front End Entirely Negative
– 5.2V
5V
+
– 5V
+
5V
LT1719S8
LT1719S8
V
V
V
V
IN
CC
EE
CC
EE
, 3V
3V
3V
OUT
+ V
GND
+ V
GND
1719 F01
S
S

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