ltc1748cfw-trpbf Linear Technology Corporation, ltc1748cfw-trpbf Datasheet

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ltc1748cfw-trpbf

Manufacturer Part Number
ltc1748cfw-trpbf
Description
14-bit, 80msps Low Noise Adc
Manufacturer
Linear Technology Corporation
Datasheet
FEATURES
BLOCK DIAGRA
APPLICATIO S
, LTC and LT are registered trademarks of Linear Technology Corporation.
Sample Rate: 80Msps
76.3dB SNR and 90dB SFDR (3.2V Range)
72.6dB SNR and 90dB SFDR (2V Range)
No Missing Codes
Single 5V Supply
Power Dissipation: 1.4W
Selectable Input Ranges: 1V or 1.6V
240MHz Full Power Bandwidth S/H
Pin Compatible Family
25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)
50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)
65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)
80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)
48-Pin TSSOP Package
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ANALOG INPUT
DIFFERENTIAL
4.7 F
1V
SENSE
U
A
A
V
IN
IN
CM
+
2.35V
SELECT
RANGE
W
REF
BUFFER
80Msps, 14-Bit ADC with a 2V Differential Input Range
AMP
S/H
DIFF AMP
0.1 F
REFLB
1 F
PIPELINED ADC
14-BIT
14-Bit, 80Msps Low Noise ADC
REFHA
DESCRIPTIO
The LTC
verter designed for digitizing high frequency, wide dy-
namic range signals. Pin selectable input ranges of 1V
and 1.6V along with a resistor programmable mode
allow the LTC1748’s input range to be optimized for a wide
variety of applications.
The LTC1748 is perfect for demanding communications
applications with AC performance that includes 76.3dB
SNR and 90dB spurious free dynamic range. Ultralow jitter
of 0.15ps
excellent noise performance. DC specs include 3LSB INL
and no missing codes.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic systems. The ENC and ENC inputs may be
driven differentially from PECL, GTL and other low swing
logic families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to any low voltage
DSPs or FIFOs.
The TSSOP package with a flow-through pinout simplifies
the board layout.
4.7 F
REFLA
1 F
®
0.1 F
RMS
1748 is an 80Msps, sampling 14-bit A/D con-
REFHB
ENCODE INPUT
DIFFERENTIAL
allows undersampling of IF frequencies with
CORRECTION
LOGIC AND
REGISTER
ENC
SHIFT
CONTROL LOGIC
ENC
U
14
MSBINV
LATCHES
OUTPUT
OE
GND
OV
OGND
V
1748 BD
DD
DD
OF
D13
D0
CLKOUT
0.1 F
1 F
1 F
0.1 F
LTC1748
1 F
0.5V
TO 5V
5V
1748fa
1

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ltc1748cfw-trpbf Summary of contents

Page 1

... LTC1744 (14-Bit), LTC1743 (12-Bit) 65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit) 80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit) 48-Pin TSSOP Package U APPLICATIO S Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems , LTC and LT are registered trademarks of Linear Technology Corporation. W BLOCK DIAGRA + DIFFERENTIAL ANALOG INPUT – A ...

Page 2

... < Sample Mode ENC < ENC Hold Mode ENC > ENC – + 1.5V < < INFORMATION ORDER PART TOP VIEW NUMBER OGND LTC1748CFW 46 D13 45 D12 LTC1748IFW 44 D11 D10 OGND 37 GND 36 GND 35 D6 ...

Page 3

ACCURACY SYMBOL PARAMETER SNR Signal-to-Noise Ratio SFDR Spurious Free Dynamic Range S/( Signal-to-(Noise + Distortion) Ratio THD Total Harmonic Distortion IMD Intermodulation Distortion Sample-and-Hold Bandwidth TER AL REFERE CE ...

Page 4

LTC1748 U U DIGITAL I PUTS A D DIGITAL OUTPUTS operating temperature range, otherwise specifications are at T SYMBOL PARAMETER V High Level Input Voltage IH V Low Level Input Voltage IL I Digital Input Current IN C Digital Input ...

Page 5

ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: When these pin voltages are ...

Page 6

LTC1748 W U TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT, Input Frequency = 30.068MHz, –10dB, 3.2V Range –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 ...

Page 7

W U TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT, Input Frequency = 69.1MHz, –10dB, 3.2V Range –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 ...

Page 8

LTC1748 W U TYPICAL PERFOR A CE CHARACTERISTICS SFDR vs Input Frequency and Amplitude, 3.2V Range, 2nd and 3rd Harmonic 100 –20dB 95 –10dB 90 –6dB 85 80 –1dB ...

Page 9

W U TYPICAL PERFOR A CE CHARACTERISTICS Offset and Gain Error vs Temperature 8 6 GAIN ERROR –2 –4 –6 –8 – 50 –30 –10 10 TEMPERATURE ( CTIO S SENSE ...

Page 10

LTC1748 DIAGRA • N ANALOG INPUT ENC t 7 DATA t 6 CLKOUT DATA U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus ...

Page 11

U U APPLICATIO S I FOR ATIO Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in ...

Page 12

LTC1748 U U APPLICATIO S I FOR ATIO In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output ...

Page 13

U U APPLICATIO S I FOR ATIO Input Drive Impedance As with all high performance, high speed ADCs the dy- namic performance of the LTC1748 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source ...

Page 14

LTC1748 U U APPLICATIO S I FOR ATIO mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener- ate the differential reference levels needed by the internal ADC circuitry. An external bypass ...

Page 15

U U APPLICATIO S I FOR ATIO ANALOG INPUT 0.1 F CLOCK INPUT 50 ENC THRESHOLD 2V ENC 0.1 F Figure 8a. Single-Ended ENC Drive, Not Recommended for Low Jitter Any noise present on the encode signal ...

Page 16

LTC1748 U U APPLICATIO S I FOR ATIO At sample rates slower than 80Msps the duty cycle can vary from 50% as long as each half cycle is at least 6ns. The lower limit of the LTC1748 sample rate is ...

Page 17

U U APPLICATIO S I FOR ATIO OV can be powered with any voltage up to 5V. The logic DD outputs will swing between OGND and OV Output Enable The outputs may be disabled with the output enable pin, OE. ...

Page 18

LTC1748 U U APPLICATIO S I FOR ATIO 1748fa ...

Page 19

... APPLICATIO S I FOR ATIO Silkscreen Top Layer 2 GND Plane Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights ...

Page 20

... Pin Compatible with the LTC1748 Pin Compatible with the LTC1748 Rail-to-Rail Input and Output www.linear.com 7.9 – 8.3 (.311 – .327) 1.20 (.0473) MAX -T- .10 C FW48 TSSOP 0502 0.05 – 0.15 (.002 – .006) 1748fa LT/TP 1103 1K REV A • PRINTED IN THE USA LINEAR TECHNOLOGY CORPORATION 2003 ...

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