ltc1744 Linear Technology Corporation, ltc1744 Datasheet - Page 17

• Manufacturer Part Number: ltc1744
• Description: 14-bit, 50msps Adc
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
3. If the ADC is clocked with a sinusoidal signal, filter the
4. Balance the capacitance and series resistance at both
The encode inputs have a common mode range of 1.8V to
V
single-ended drive.
DD
coupled use a higher turns ratio to increase the
amplitude.
encode signal to reduce wideband noise.
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
. Each input may be driven from ground to V
V
THRESHOLD
Figure 8a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
U
= 2V
0.1 F
U
2V
ENC
ENC
W
LTC1744
1744 F08a
U
DD
for
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC1744 is 50Msps. For
the ADC to operate properly the ENCODE signal should
have a 50% ( 5%) duty cycle. Each half cycle must have
at least 9.5ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise
50% duty cycle is easy with differential sinusoidal drive
using a transformer or using symmetric differential logic
such as PECL or LVDS. When using a single-ended
ENCODE signal asymmetric rise and fall times can result
in duty cycles that are far from 50%.
At sample rates slower than 50Msps the duty cycle can
vary from 50% as long as each half cycle is at least 9.5ns.
The lower limit of the LTC1744 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC1744 is 1Msps.
Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
MC100LVELT22
D0
3.3V
Q0
Q0
130
83
3.3V
130
83
ENC
ENC
LTC1744
LTC1744
1744 F08b
17
1744f