ltc1064-1cn-pbf Linear Technology Corporation, ltc1064-1cn-pbf Datasheet - Page 5

• Manufacturer Part Number: ltc1064-1cn-pbf
• Description: Low Noise, 8th Order, Clock Sweepable Elliptic Lowpass Filter
• Manufacturer: Linear Technology Corporation

PI FU CTIO S
operation both pins should be tied to one half supply
(Figure 2). Also Pin 8 and Pin 10, although they are not
internally connected should be tied to analog ground or
system ground. This improves the clock feedthrough
performance.
V
bypassed with a 0.1µF capacitor to an adequate analog
ground. Low noise, nonswitching power supplies are
recommended. To avoid latchup when the power supplies
exhibit high turn-on transients, a 1N5817 Schottky diode
should be added from the V
(Figure 1).
INV A, R(h, I) (Pins 7, 14): A very short connection
between Pin 14 and Pin 7 is recommended. This connec-
tion should be preferably done under the IC package. In a
TYPICAL APPLICATIO S
+
, V
U
1N5817
V
+
–
0.1µF
(Pins 4, 12): The V
V
Figure 3. Level Shifting the Input T
for Single Supply Operation, V+ >6V.
V
Figure 1. Using Schottky Diodes to Protect
the IC from Power Supply Spikes
IN
U
+
V
IN
5k
5k
0.1µF
U
1
2
3
4
5
6
7
1
2
3
4
5
6
7
INV C
V
AGND
V
AGND
COMP1*
INV A
INV C
V
AGND
V
AGND
COMP1*
INV A
IN
+
IN
+
LTC1064-1
LTC1064-1
(Pin Numbers Refer to the 14-Pin Package)
COMP2*
COMP2*
R(h, I)
R(h, I)
V
V
f
f
OUT
OUT
CLK
CLK
NC
NC
NC
NC
V
V
+
–
–
+
14
13
12
11
10
9
8
14
13
12
11
10
9
8
and V
and V
U
5k 1µF
1N5817
V
+
V
–
2.2k
–
OUT
2
V
L Clock
OUT
pins should be
pins to ground
T
LEVEL
2
L
0.1µF
1064 F03
V
1064 F01
–
breadboard, use a one inch, or less, shielded coaxial cable;
the shield should be grounded. In a PC board, use a one
inch trace or less; surround the trace by a ground plane.
NC (Pins 8, 10): The “no connection” pins preferably
should be grounded.
f
1.4V. For ±8V and 0V to 5V supplies the logic threshold
levels are 2.2V and 3V respectively. The logic threshold
levels vary ±100mV over the full military temperature
range. The recommended duty cycle of the input clock is
50% although for clock frequencies below 500kHz the
clock “on” time can be as low as 200ns. The maximum
clock frequency for ±5V supplies is 4MHz. For ±7V sup-
plies and above, the maximum clock frequency is 5MHz.
Do not allow the clock levels to exceed the power supplies.
For clock level shifting (see Figure 3).
CLK
Figure 4. Buffering the Filter Output. The Buffer Op Amp
Should Not Share the LTC1064-1 Power Lines.
(Pin 11): For ±5V supplies the logic threshold level is
V
0.1µF
+
= 15V
V
Figure 2. Single Supply Operation. If Fast Power Up
or Down Transients are Expected, Use a 1N5817
Schottky Diode Between Pin 4 and Pin 5.
IN
RECOMMENDED OP AMPS:
LT1022, LT318, LT1056
0.1µF
0.1µF
1
2
3
4
5
6
7
INV C
V
AGND
V
AGND
COMP1*
INV A
IN
+
5k
LTC1064-1
V
IN
5k
COMP2*
R(h, I)
V
f
V
OUT
CLK
NC
NC
V
+
/2
–
14
13
12
11
10
9
8
1
2
3
4
5
6
7
INV C
V
AGND
V
AGND
COMP1*
INV A
IN
+
10k
LTC1064-1
0.1µF
COMP2*
R(h, I)
V
LTC1064-1
f
OUT
CLK
NC
NC
V
10k
–
+
–
14
13
12
11
10
9
8
POWER SOURCE
V
+
0.1µF
0.1µF
1064 F02
V
–
0V TO 10V
V
OUT
V
OUT
1064 F04
10641fa
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