ltc1196-2bcs8-trpbf Linear Technology Corporation, ltc1196-2bcs8-trpbf Datasheet - Page 16

• Manufacturer Part Number: ltc1196-2bcs8-trpbf
• Description: 8-bit, So-8, 1msps Adcs With Auto-shutdown Options
• Manufacturer: Linear Technology Corporation

LTC1196/LTC1198
APPLICATIONS INFORMATION
Dummy Bits
The last 2 bits of the input word following the MUX Ad-
dress are dummy bits. Either bit can be a “logical one” or
a “logical zero.” These 2 bits allow the ADC 2.5 clocks to
acquire the input signal after the channel selection.
A/D Conversion Result
Both the LTC1196 and the LTC1198 have the A/D conver-
sion result appear on the D
Operating Sequence in Figures 1 and 2). Data on the D
line is updated on the rising edge of the CLK line. The D
data should also be captured on the rising CLK edge by the
digital systems. Data on the D
minimum time of t
to occur (see Figure 3).
Unipolar Transfer Curve
The LTC1196/LTC1198 are permanently confi gured for
unipolar only. The input span and code assignment for this
conversion type are shown in the following fi gures.
16
Figure 3. Voltage Waveform for D
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
D
•
•
•
CLK
OUT
Unipolar Transfer Curve
V
hDO
t
hDO
IH
t
dDO
(30ns at 5V) to allow the capture
OUT
OUT
OUT
line after two null bits (see
Delay Time, t
line remains valid for a
1196/98 TC03
dDO
V
V
and t
OH
OL
1196/98 AI04
hDO
OUT
OUT
V
IN
Operation with D
The LTC1198 can be operated with D
together. This eliminates one of the lines required to com-
municate to the digital systems. Data is transmitted in both
directions on a single wire. The pin of the digital systems
connected to this data line should be confi gurable as either
an input or an output. The LTC1198 will take control of the
data line and drive it low on the 5th falling CLK edge after
the start bit is received (see Figure 4). Therefore the port
line of the digital systems must be switched to an input
before this happens to avoid a confl ict.
REDUCING POWER CONSUMPTION
The LTC1196/LTC1198 can sample at up to a 1MHz rate,
drawing only 50mW from a 5V supply. Power consumption
can be reduced in two ways. Using a 3V supply lowers the
power consumption on both devices by a factor of fi ve,
to 10mW. The LTC1198 can reduce power even further
because it shuts down whenever it is not converting.
Figure 5 shows the supply current versus sample rate for
the LTC1196 and LTC1198 on 3V and 5V. To achieve such
a low power consumption, especially for the LTC1198,
several things must be taken into consideration.
Shutdown (LTC1198)
Figure 2 shows the operating sequence of the LTC1198.
The converter draws power when the CS pin is low and
powers itself down when that pin is high. For lowest power
consumption in shutdown, the CS pin should be driven
with CMOS levels (0V to V
of the converter will not draw current.
OUTPUT CODE
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
•
•
•
IN
Unipolar Output Code
and D
INPUT VOLTAGE
V
V
REF
REF
1LSB
OUT
CC
0V
– 1LSB
– 2LSB
•
•
•
) so that the CS input buffer
Tied Together
INPUT VOLTAGE
(V
REF
4.9805V
4.9609V
0.0195V
IN
= 5.000V)
0V
•
•
•
and D
1196/98 AI05
OUT
119698fa
tied