mc28r36m Centellax, mc28r36m Datasheet - Page 4

• Manufacturer Part Number: mc28r36m
• Description: Clock Recovery Unit Cru Module
• Manufacturer: Centellax

The MC28R36M has two loops with two separate inputs -- one for training the loop to the right frequency,
and the other for phase locking the loop to the actual data. Refer to page 3 for block diagram. The part
requires a 1/4 rate clock for training the CRU. Once the loop is trained, the input should be switched over
to the data input by setting the LOCK pin (pin 1) High (or 0V).
1. Connect both data and reference inputs to the device. The reference clock should be 1/4 of the data
rate. For example, if data rate is 27.95 Gbps, then reference clock is 6.9875 GHz (sine or square). Make
sure that the LOCK pin (pin 1) is set to Low, or -3.3V, or left open (it defaults to logic state Low).
2. Monitor the output frequency to see if the loop has locked to the desired frequency, which should be
half-rate. For this example, the loop is locked if CKO is 13.975 GHz.
3. Once the loop is locked (i.e. trained), switch the LOCK pin to High, or 0V, to lock onto the data input.
*The MC28R36M may also be trained using 1/8 or 1/16 of the data rate as the reference clock input; however, the VCO capture range will be
reduced.
3
All measurements in inches (mm)
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CENTELLAX
Specifications subject to change without notice. Copyright © 2001-2009 Centellax, Inc. Printed in USA. 4 Feb 2009. smd-00021 rev B.