ltc2291cup-trpbf Linear Technology Corporation, ltc2291cup-trpbf Datasheet

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ltc2291cup-trpbf

Manufacturer Part Number
ltc2291cup-trpbf
Description
Ltc2292 - Dual 12-bit, 40msps Low Power 3v Adcs
Manufacturer
Linear Technology Corporation
Datasheet
FEATURES
TYPICAL APPLICATIO
ANALOG
ANALOG
INPUT A
INPUT B
APPLICATIO S
CLK A
CLK B
Integrated Dual 12-Bit ADCs
Sample Rate: 65Msps/40Msps/25Msps
Single 3V Supply (2.7V to 3.4V)
Low Power: 400mW/235mW/150mW
71.3dB SNR
90dB SFDR
110dB Channel Isolation at 100MHz
Multiplexed or Separate Data Bus
Flexible Input: 1V
575MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)
64-Pin (9mm × 9mm) QFN Package
Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
CLOCK/DUTY CYCLE
CLOCK/DUTY CYCLE
+
+
INPUT
INPUT
CONTROL
CONTROL
S/H
S/H
U
P-P
to 2V
PIPELINED
ADC CORE
PIPELINED
ADC CORE
P-P
12-BIT
12-BIT
Range
U
DRIVERS
DRIVERS
OUTPUT
OUTPUT
DESCRIPTIO
The LTC
40Msps/25Msps, low power dual 3V A/D converters de-
signed for digitizing high frequency, wide dynamic range
signals. The LTC2293/LTC2292/LTC2291 are perfect for
demanding imaging and communications applications
with AC performance that includes 71.3dB SNR and 90dB
SFDR for signals at the Nyquist frequency.
DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSB
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic. An optional multiplexer allows both channels to
share a digital output bus.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
All other trademarks are the property of their respective owners.
229321 TA01
LTC2293/LTC2292/LTC2291
, LTC and LT are registered trademarks of Linear Technology Corporation.
OV
D11A
D0A
OGND
MUX
OV
D11B
D0B
OGND
• •
• •
DD
DD
®
Dual 12-Bit, 65/40/25Msps
2293/LTC2292/LTC2291 are 12-bit 65Msps/
Low Power 3V ADCs
U
RMS
LTC2293: SNR vs Input Frequency,
72
71
70
69
68
.
0
–1dB, 2V Range, 65Msps
50
INPUT FREQUENCY (MHz)
100
150
229321 TA02
229321fa
200
1

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ltc2291cup-trpbf Summary of contents

Page 1

... A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high perfor- mance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners ...

Page 2

... DA1 43 DA0 LTC2293IUP LTC2292CUP 40 OFB 39 DB11 LTC2292IUP 38 DB10 37 DB9 LTC2291CUP 36 DB8 35 DB7 LTC2291IUP 34 DB6 33 DB5 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: The ● denotes the specifications which apply over the full operating = 25° ...

Page 3

ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are 25°C. (Note 4) A SYMBOL PARAMETER + V Analog Input Range (A – ...

Page 4

LTC2293/LTC2292/LTC2291 TER AL REFERE CE CHARACTERISTICS PARAMETER V Output Voltage CM V Output Tempco CM V Line Regulation CM V Output Resistance DIGITAL I PUTS A D DIGITAL OUTPUTS full operating temperature range, ...

Page 5

W U POWER REQUIRE E TS range, otherwise specifications are at T SYMBOL PARAMETER CONDITIONS V Analog Supply (Note 9) DD Voltage OV Output Supply (Note 9) DD Voltage IV Supply Current Both ADCs Power Dissipation ...

Page 6

LTC2293/LTC2292/LTC2291 W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2293/LTC2292/LTC2291: Crosstalk vs Input Frequency –100 –105 –110 –115 –120 –125 –130 100 INPUT FREQUENCY (MHz) 229321 G01 LTC2293: 8192 Point FFT 5MHz, –1dB, 2V ...

Page 7

W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2293: SNR vs Input Frequency, –1dB, 2V Range, 65Msps 100 150 200 INPUT FREQUENCY (MHz) 229321 G10 LTC2293: SNR and SFDR vs Clock Duty Cycle, 65Msps ...

Page 8

LTC2293/LTC2292/LTC2291 W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2292: Typical INL, 2V Range, 40Msps 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 –1.00 0 1024 2048 3072 4096 CODE 229321 G18 LTC2292: 8192 Point FFT 30MHz, –1dB, 2V ...

Page 9

W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2292: SFDR vs Input Frequency, –1dB, 2V Range, 40Msps 100 100 150 200 INPUT FREQUENCY (MHz) 229321 G27 LTC2292: SFDR vs Input Level, f ...

Page 10

LTC2293/LTC2292/LTC2291 W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2291: 8192 Point FFT 30MHz, –1dB, 2V Range, IN 25Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 ...

Page 11

W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2291: SFDR vs Input Level 5MHz, 2V Range, 25Msps IN 120 dBFS 110 100 90 80 dBc 70 60 90dBc SFDR 50 REFERENCE LINE –60 –50 – 40 ...

Page 12

LTC2293/LTC2292/LTC2291 CTIO S MUX (Pin 21): Digital Output Multiplexer Control. If MUX is High, Channel A comes out on DA0-DA11, OFA; Channel B comes out on DB0-DB11, OFB. If MUX is Low, the output busses ...

Page 13

U U FUNCTIONAL BLOCK DIAGRA + A IN INPUT FIRST PIPELINED S/H ADC STAGE – 1.5V CM REFERENCE 2.2µF RANGE SELECT REF BUF SENSE Figure 1. Functional Block Diagram (Only One Channel is Shown) LTC2293/LTC2292/LTC2291 W SECOND ...

Page 14

LTC2293/LTC2292/LTC2291 DIAGRA ANALOG N INPUT t H CLK – 5 D0-D11, OF ANALOG A INPUT A ANALOG B INPUT B t CLKA = CLKB = MUX A – ...

Page 15

U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other ...

Page 16

LTC2293/LTC2292/LTC2291 U U APPLICATIO S I FOR ATIO sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2293/LTC2292/ LTC2291 have two phases of operation, determined by the state of ...

Page 17

U U APPLICATIO S I FOR ATIO capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If ...

Page 18

LTC2293/LTC2292/LTC2291 U U APPLICATIO S I FOR ATIO 2.2µF HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG + + INPUT CM 12pF – – 25Ω Figure 4. Differential Drive with an Amplifier Figure 5 shows a single-ended input circuit. The imped- ance ...

Page 19

U U APPLICATIO S I FOR ATIO Reference Operation Figure 9 shows the LTC2293/LTC2292/LTC2291 refer- ence circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two ...

Page 20

LTC2293/LTC2292/LTC2291 U U APPLICATIO S I FOR ATIO 4.7µF FERRITE 1k 0.1µF SINUSOIDAL CLOCK INPUT 50Ω 1k NC7SVU04 Figure 11. Sinusoidal Single-Ended CLK Drive The noise performance of the LTC2293/LTC2292/LTC2291 can depend on the clock signal quality as much as ...

Page 21

U U APPLICATIO S I FOR ATIO Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2293/LTC2292/ LTC2291 is 65Msps (LTC2293), 40Msps (LTC2292), and 25Msps (LTC2291). For the ADC to operate properly, the CLK signal should have a ...

Page 22

LTC2293/LTC2292/LTC2291 U U APPLICATIO S I FOR ATIO ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. Lower OV voltages will also help reduce interference DD from the digital outputs. Data Format Using the ...

Page 23

U U APPLICATIO S I FOR ATIO Grounding and Bypassing The LTC2293/LTC2292/LTC2291 requires a printed cir- cuit board with a clean, unbroken ground plane. A multi- layer board with an internal ground plane is recom- mended. Layout for the printed ...

Page 24

LTC2293/LTC2292/LTC2291 U U APPLICATIO S I FOR ATIO 229321fa ...

Page 25

U U APPLICATIO S I FOR ATIO LTC2293/LTC2292/LTC2291 W U Silkscreen Top Top Side 229321fa 25 ...

Page 26

LTC2293/LTC2292/LTC2291 U U APPLICATIO S I FOR ATIO Inner Layer 2 GND Bottom Side Inner Layer 3 Power 229321fa ...

Page 27

... SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC2293/LTC2292/LTC2291 ...

Page 28

... BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz 12.5dB, 50Ω Single Ended RF and LO Ports www.linear.com ● 229321fa RD/LT 0207 REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2004 ...

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