ltc2428 Linear Technology Corporation, ltc2428 Datasheet - Page 15

• Manufacturer Part Number: ltc2428
• Description: 4-/8-channel 20-bit ?power No Latency Delta-sigma Adc
• Manufacturer: Linear Technology Corporation

APPLICATIONS
LOW. The multiplexer should be programmed after the
previous conversion is complete. In order to guarantee the
conversion is complete, the multiplexer addressing should
be delayed a minimum t
60Hz notch) after the data out is read.
While the multiplexer is being programmed, the ADC is in
the sleep state. Once the MUX addressing is complete, the
data from the preceding conversion can be read. A new
conversion cycle is initiated following the data read cycle
with the analog input tied to the newly selected channel.
Table 3. Logic Table for Channel Selection
*Not used for the LTC2424.
Frequency Rejection Selection (F
The LTC2424/LTC2428 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz 2% or 60Hz 2%. For
60Hz rejection, F
(Pin 1) while for 50Hz rejection the F
connected to V
The selection of 50Hz or 60Hz rejection can also be made
by driving F
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2424/
LTC2428 can operate with an external conversion clock.
CHANNEL STATUS
All Off
CH4*
CH5*
CH6*
CH7*
CH0
CH1
CH2
CH3
O
to an appropriate logic level. A selection
CC
O
(Pin 2).
(Pin 26) should be connected to GND
U
EN
CONV
0
1
1
1
1
1
1
1
1
INFORMATION
U
(approximately 133ms for a
D2
X
0
0
0
0
1
1
1
1
O
W
Pin Connection)
O
D1
pin should be
X
0
0
1
1
0
0
1
1
U
D0
X
0
1
0
1
0
1
0
1
The converter automatically detects the presence of an
external clock signal at the F
oscillator. The frequency f
be at least 2560Hz (1Hz notch frequency) to be detected.
The external clock signal duty cycle is not significant as
long as the minimum and maximum specifications for the
high and low periods t
While operating with an external conversion clock of a
frequency f
than 110dB normal mode rejection in a frequency range
f
rejection as a function of the input frequency deviation
from f
Whenever an external clock is not present at the F
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2424/
LTC2428 operation will not be disturbed if the change of
conversion clock source occurs during the sleep state or
during the data output state while the converter uses an
external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside specifications but the following conver-
sions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
EOSC
Figure 5. LTC2424/LTC2428 Normal Mode Rejection When
Using an External Oscillator of Frequency f
/2560 4% and its harmonics. The normal mode
EOSC
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
–100
–110
–120
–130
–140
–60
–70
–80
–90
/2560 is shown in Figure 5.
EOSC
–12
, the LTC2424/LTC2428 provide better
–8
HEO
–4
LTC2424/LTC2428
EOSC
and t
O
0
pin and turns off the internal
of the external signal must
LEO
4
are observed.
8
24248 F05
EOSC
12
O
15
pin the