ltc3703egn-trpbf Linear Technology Corporation, ltc3703egn-trpbf Datasheet - Page 14

• Manufacturer Part Number: ltc3703egn-trpbf
• Description: 100v Synchronous Switching Regulator Controller
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC3703
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gate-
to-drain capacitance. The flat portion of the curve is the
result of the Miller multiplication effect of the drain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-to-
source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V
adjusted for different V
ratio of the application V
values. A way to estimate the C
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated V
specified. C
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C
and C
parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
14
appropriate breakdown specification. Since many high
voltage MOSFETs have higher threshold voltages (typi-
cally, V
with a 9V to 15V gate drive supply (DRV
For maximum efficiency, on-resistance R
capacitance should be minimized. Low R
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 9).
V
GS
OS
GS(MIN)
are specified sometimes but definitions of these
C
MILLER
MILLER
a
Figure 9. Gate Charge Characteristic
MILLER EFFECT
≥ 6V), the LTC3703 is designed to be used
= (Q
Q
IN
B
is the most important selection criteria
U
– Q
A
)/V
b
DS
DS
U
DS
voltages by multiplying by the
to the curve specified V
DS
MILLER
drain voltage, but can be
W
V
+
GS
–
term is to take the
V
DS(ON)
CC
DS(ON)
pin).
+
–
DS
U
minimizes
V
and input
3703 F09
DS
V
voltage
IN
RSS
DS
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
where δ is the temperature dependency of R
the effective top driver resistance (approximately 2Ω at
V
in drain potential in the particular application. V
data sheet specified typical gate threshold voltage speci-
fied in the power MOSFET data sheet at the specified drain
current. C
gate charge curve from the MOSFET data sheet and the
technique described above.
Both MOSFETs have I
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
high current efficiency generally improves with larger
MOSFETs, while for V
rapidly increase to the point that the use of a higher
R
efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
typically varies from 0.005/°C to 0.01/°C depending on
the particular MOSFET used.
GS
DS(ON)
P
P
MainSwitchDutyCycle
SynchronousSwitchDutyCycle
MAIN
SYNC
= V
MILLER
device with lower C
=
=
MILLER
V
⎡
⎢
⎢
⎣
V
V
V
IN
OUT
V
IN
IN
CC
), V
2
−
V
I
MAX
IN
–
(
is the calculated capacitance using the
V
IN
2
I
MAX
1
OUT
V
is the drain potential and the change
TH IL
2
(
R losses while the topside N-channel
R R
( )
)
(
DS(ON)
DR
I
2
IN
MAX
(
1
)(
+
MILLER
> 25V, the transition losses
=
+
C
) (
V
V
δ
MILLER
2
TH IL
vs temperature curve, and
V
OUT
)
IN
R
1
1 δ
( )
+
DS ON
actually provides higher
(
=
⎤
⎥
⎥ ⎥
⎦
)
) •
R
( )
f
V
DS N
)
IN
+
(
0
–
V
IN
DS(ON)
V
)
IN
OUT
TH(IL)
< 25V, the
, R
is the
DR
3703fa
is