ltc4241cgn-trpbf Linear Technology Corporation, ltc4241cgn-trpbf Datasheet - Page 11

• Manufacturer Part Number: ltc4241cgn-trpbf
• Description: Pci-bus With 3.3v Auxiliary Hot Swap Controller
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
The current in each pass transistor increases until it
reaches the current limit for each supply. Each supply is
allowed to power up at the rate dV/dt = 60 A/C1 or as
determined by the current limit and the load capacitance
on the supply line, whichever is slower. Current limit faults
are ignored while the TIMER pin voltage is ramping up and
is less than 0.9V below 12V
voltages are within tolerance, the PWRGD pin will pull low.
Power-Down Sequence for PCI Power Supplies
When the ON pin is pulled low, a power-down sequence
begins for all the PCI power supplies (Figure 3).
Internal switches are connected to each of the output
supply voltage pins to discharge the load capacitors to
ground. The TIMER pin is immediately pulled low and the
internal 12V and –12V switches are turned off. The GATE
pin is pulled to ground by an internal 200 A current
source. This turns off the external pass transistors in a
controlled manner and prevents the load current on the
3.3V and 5V supplies from going to zero instantaneously
and glitching the power supply voltages. When any of the
output voltages dips below its threshold, the PWRGD pin
pulls high.
5V
3V
OUT
OUT
10V/DIV
10V/DIV
10V/DIV
10V/DIV
10V/DIV
PWRGD
12V
Figure 2. Normal Power-Up Sequence
V
5V/DIV
5V/DIV
5V/DIV
5V/DIV
TIMER
FAULT
EEOUT
GATE
OUT
ON
U
U
IN
10ms/DIV
. Once all four PCI supply
W
4241 F02
U
Timer
During a power-up sequence for the PCI power supplies,
a 22 A current source is connected to the TIMER pin and
current limit faults are ignored until the voltage ramps to
within 0.9V of 12V
up a PCI slot that can accommodate boards with a wide
range of capacitive loads on the supplies. The power-up
time for any one of the four outputs will be:
For example, for C
I
substituting the variables in the above equation with the
appropriate values, the turn-on time for the other three
outputs can be calculated. The timer period should be set
longer than the maximum supply turn-on time but short
enough to not exceed the maximum safe operating area of
the pass transistor during a short-circuit. The timer period
is given by:
LOAD
t
t
ON
TIMER
5V
3V
= 5A, the 5V
OUT
OUT
2 •
10V/DIV
10V/DIV
10V/DIV
10V/DIV
10V/DIV
PWRGD
12V
Figure 3. Normal Power-Down Sequence
V
5V/DIV
5V/DIV
5V/DIV
5V/DIV
TIMER
FAULT
EEOUT
GATE
C
OUT
ON
I
C
LIMIT
TIMER
LOAD
22
IN
LOAD
OUT
. This feature allows the chip to power
–
•
•
A
I
11 1
V
LOAD
OUT
= 2000 F, V
turn-on time will be ~10ms. By
.
V
10ms/DIV
OUT
LTC4241
= 5V, I
4241 F03
LIMIT
sn4241 4241f
11
= 7A,