ltc4001 Linear Technology Corporation, ltc4001 Datasheet - Page 15

• Manufacturer Part Number: ltc4001
• Description: 2a Synchronous Buck Li-ion Charger
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
Battery charging current continues to drop as the V
rises, dropping to zero at V
in the LTC4001 is very low when charge current is highest,
power dissipation is also very low.
Thermal Calculations (PWM and Trickle Charging)
The LTC4001 operates as a linear charger when condition-
ing (trickle) charging a battery and operates as a high rate
buck battery charger at all other times. Power dissipation
should be determined for both operating modes.
For linear charger mode:
where I
Worst-case dissipation occurs for V
and maximum quiescent and trickle charge current. For
example with 5.5V maximum input voltage and 65mA
worst case trickle charge current, and 2mA worst-case
chip quiescent current:
LTC4001 power dissipation is very low if a current limited
wall adapter is used and allowed to enter current limit.
When the wall adapter is in current limit, the voltage drop
across the LTC4001 charger is:
where I
the on resistance of the topside PMOS switch.
P
P
V
D
D
DROP
= (V
= (5.5 – 0) • 65mA + 5.5 • 2mA = 368.5mW
IN
LIMIT
= I
is V
IN
LIMIT
– V
is the wall adapter current limit and R
IN
BAT
current consumed by the IC.
• R
U
) • I
PFET
TRIKL
U
I
BAT
V
FLOAT.
IN
+ V
Because the voltage drop
IN
LINEAR CHARGING
• I
W
BAT
IN
V
I
ADAPTER
TRICKLE
= 0, maximum V
Figure 5. Charging Characteristic
U
PFET
V
TRIKL
BAT
IN
is
WALL ADAPTER IN CURRENT LIMIT
,
V
BAT
The total LTC4001 power dissipation during current lim-
ited charging is:
where I
current flowing through the IDET and PROG programming
pins. Maximum dissipation in this mode occurs with the
highest V
(which is very close to V
I
highest programming current I
Assume the LTC4001 is programmed for 2A charging and
200mA IDET and that a 1.5A wall adapter is being used:
I
V
then:
and:
Power dissipation in buck battery charger mode may be
estimated from the dissipation curves given in the Typical
Performance Characteristics section of the data sheet.
This will slightly overestimate chip power dissipation
because it assumes all loss, including loss from external
components, occurs within the chip.
IN
LIMIT
V
BAT
BAT
, highest PMOS on resistance R
P
V
P
• 1500mA = 312mW
I
D
DROP
D
LIMIT
+ V
≈ V
= 1500mA, R
= (4.242V + 0.1905V) • (2mA + 4mA) + 0.1905V
= (V
DROP
IN
FLOAT
= 1500mA • 127mΩ = 190.5mV
BAT
BAT
is the chip quiescent current and I
that keeps the wall adapter in current limit
+ V
= 4.242V
DROP
PFET
V
CHARGING
FLOAT
PWM
) • (I
= 127mΩ, I
FLOAT
4001 F05
IN
+ I
), highest quiescent current
P
P
.
) + V
PFET
IN
= 2mA, I
DROP
, highest I
LTC4001
• I
P
LIMIT
= 4mA and
P
LIMIT
15
is total
and
4001f