ltc4151 Linear Technology Corporation, ltc4151 Datasheet - Page 10

• Manufacturer Part Number: ltc4151
• Description: High Voltage I2c Current And Voltage Monitor
• Manufacturer: Linear Technology Corporation

LTC4151/LTC4151-1
APPLICATIONS INFORMATION
Using Optoisolators with LTC4151-1
The LTC4151-1 splits the SDA line into SDAI (input)
and SDAO (inverted output) for convenience of opto-
coupling with a host controller that sits at a differ-
ent ground level. When using optoisolators with the
LTC4151-1, connect the SDAI to the output of the
incoming optocoupler and connect the SDAO to the anode
of the outgoing optocoupler (see Figure 9). With the
outgoing optocoupler clamping SDAO and internal 6V
(5.5V minimum) clamps on SDAI and SCL, the pull-up
resistors on these three pins can be directly connected
to V
SDAO), the need for a separate low voltage supply for
pull-ups is eliminated.
Start and Stop Conditions
When the I
in the high state. A bus master signals the beginning of a
transmission with a Start condition by transitioning SDA
from high to low while SCL stays high. When the master
has fi nished communicating with the slave, it issues a
Stop condition by transitioning SDA from low to high
while SCL stays high. The bus is then free for another
transmission.
10
IN
V
IN
. In this way (with SDAO rather than conventional
2
C bus is idle, both SCL and SDA must remain
2
3
4
V
ADR1
ADR0
IN
SENSE
Figure 9. Optoisolation of the I
1
+
LTC4151-1
0.02Ω
GND
R
S
9
SENSE
10
–
SDA0
SDAI
ADIN
SCL
6
7
8
5
R1
20k
V
ADIN
2
C Interface Between LTC4151-1 and a Microcontroller
R2
20k
R3
5k
Stuck-Bus Reset
The LTC4151/LTC4151-1 I
bus reset timer. The low conditions of the SCL and the
SDA/SDAI pins are OR’ed to start the timer. The timer is
reset when both SCL and SDA/SDAI are pulled high. If the
SCL pin or the SDA/SDAI pin is held low for over 33ms,
the stuck-bus timer will expire and the internal I
machine will be reset to allow normal communication after
the stuck-bus condition is cleared. The stuck-bus timer
can be disabled by clearing control register bit G2.
I
Nine distinct I
ing the three-state pins ADR0 and ADR1, as shown in
Table 1. Address bits a6, a5 and a4 are confi gured to
(110) and the least signifi cant bit is the R/W bit. In addi-
tion, the LTC4151 and LTC4151-1 will respond to a mass
write address (1100 110)b for writing to all LTC4151s
and LTC4151-1s, regardless of their individual address
settings.
2
C Device Addressing
8
7
6
5
1
2
3
4
MOCD207M
MOCD207M
2
1
2
3
4
5
6
7
8
C bus addresses are confi gurable us-
R4
0.5k
R5
0.5k
2
C interface features a stuck-
R6
10k
R7
10k
SCL
SDA
μ-Controller
3.3V
V
DD
41511 F09
2
C state
41511f