s29jl032j Meet Spansion Inc., s29jl032j Datasheet - Page 41
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s29jl032j
Manufacturer Part Number
s29jl032j
Description
32megabit 4m X 8-bit/2m X 16-bit Cmos 3.0volt-only, Simultaneous Read/write Flash Memory
Manufacturer
Meet Spansion Inc.
Datasheet
1.S29JL032J.pdf
(60 pages)
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11.4
11.5
11.6
January 27, 2010 S29JL032J_00_01
DQ2: Toggle Bit II
Reading Toggle Bits DQ6/DQ2
DQ5: Exceeded Timing Limits
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to
outputs for DQ2 and DQ6.
Figure 11.2 on page 40
explains the algorithm. See also
timing diagram.
Refer to
toggle bit status, it must read DQ15–DQ0 (or DQ7–DQ0 for x8-only device) at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle
bit after the first read. After the second read, the system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system
can read array data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or
erase operation. If it is still toggling, the device did not completed the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” The
RDY/BSY# pin will be in the BUSY state under this condition.
Under both these conditions, the system must write the reset command to return to the read mode (or to the
erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
D a t a
Figure 11.2 on page 40
S h e e t
Figure 17.11 on page 54
shows the toggle bit algorithm in flowchart form, and
( A d v a n c e
DQ6: Toggle Bit I on page
for the following discussion. Whenever the system initially begins reading
S29JL032J
shows the differences between DQ2 and DQ6 in graphical form.
I n f o r m a t i o n )
Figure 11.2 on page
39.
Figure 17.10 on page 53
40).
Table 11.1 on page 42
DQ2: Toggle Bit II on page 41
shows the toggle bit
to compare
41