mt36ldt3272g-6-x Micron Semiconductor Products, mt36ldt3272g-6-x Datasheet - Page 12

• Manufacturer Part Number: mt36ldt3272g-6-x
• Description: 8, 16, 32 Meg X 72 Buffered Dram Dimms
• Manufacturer: Micron Semiconductor Products

EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 1-8; notes appear below and on next page) (V
NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
8, 16, 32 Meg x 72 Buffered DRAM DIMMs
DM77_2.p65 – Rev. 3/00
AC CHARACTERISTICS
PARAMETER
READ command hold time (referenced to CAS#)
READ command setup time
Refresh period
RAS# precharge time
RAS# to CAS# precharge time
READ command hold time (referenced to RAS#)
RAS# hold time
READ-WRITE cycle time
RAS# to WE# delay time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
WE# to outputs in High-Z
WRITE command pulse width
WE# pulse width to disable outputs
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
10. A +5ns timing skew from the DRAM to the module resulted from the addition of line drivers.
11. A -2ns timing skew from the DRAM to the module resulted from the addition of line drivers.
12. A +2ns timing skew from the DRAM to the module resulted from the addition of line drivers.
13.
14. Requires that
15. If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new
16. Enables on-chip refresh and address counters.
17. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE
18. The 3ns minimum is a parameter guaranteed by design.
2. An initial pause of 100µs is required after power-up, followed by eight RAS# REFRESH cycles (RAS#-ONLY or CBR with
3. AC characteristics assume
4. V
5. In addition to meeting the transition rate specification, all input signals must transit between V
6. If CAS# and RAS# = V
7. If CAS# = V
8. Measured with a load equivalent to two TTL gates and 100pF and V
9. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not possible.
range is ensured.
WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time
the
between V
V
t
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle.
t
and then applying input data. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-
controlled) cycle.
cycle and clear the data-out buffer, CAS# must be pulsed HIGH for
or READ-MODIFY-WRITE cycles.
WCS,
AWD and
IH
IL
and V
(MIN) and V
t
REF refresh requirement is exceeded.
t
RWD,
IH
t
) in a monotonic manner.
CWD define READ-MODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data
IH
IL
, data output may contain data from the last valid READ cycle.
t
and V
AWD and
t
AA and
IL
t
(MAX) are reference levels for measuring timing of input signals. Transition times are measured
WCS,
IL
(or between V
IH
t
t
, data output is High-Z.
t
CWD are not restrictive operating parameters.
RAC are not violated.
RWD,
t
T = 2ns for -5 and 2.5ns for -6.
t
CWD and
IL
and V
t
AWD are not applicable in a LATE WRITE cycle.
IH
SYMBOL
).
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RWD
WCH
WRH
t
RWC
WCR
WHZ
RWL
WCS
t
WPZ
WRP
RCH
RRH
t
RPC
RSH
RCS
REF
WP
RP
t
T
DD
12
= +3.3V ±0.3V)
MIN
121
30
18
69
18
13
36
10
10
2
2
5
0
2
2
5
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
-5
t
CP.
MAX
OL
t
WCS applies to EARLY WRITE cycles. If
64
50
17
= 0.8V and V
BUFFERED DRAM DIMMs
MIN
145
40
20
81
20
15
43
10
12
2
2
5
0
2
2
5
8
8, 16, 32 MEG x 72
OH
-6
= 2V.
MAX
64
50
20
IH
and V
UNITS
©2000, Micron Technology, Inc.
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IL
(or between
t
WCS >
NOTES
27
28
27
10
10
26
10
10
11
16
10
10
12
t
t
WCS
RWD,