mt34013 Aeroflex Circuit Technology, mt34013 Datasheet - Page 7

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mt34013

Manufacturer Part Number
mt34013
Description
Eight Channel Arinc Decoder
Manufacturer
Aeroflex Circuit Technology
Datasheet

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Notes:-
(1)
(2)
(3)
(4)
(5)
(6)
T
t
tv
t
t
tc
t
t
t
The CHIP ENABLE line going high during the select timing resets DATA READY and terminates the read
action. Not all 3 words (or 5 bytes) need to be accessed and read termination can take place at any time.
The output timing for the 8 bit parallel bus is similar to the above but with 5 byte accesses required.
The NOT CHIP ENABLE line cannot be held permanently low (see (1)).
All timings are theoretical and are based on a load of 100pF and one standard TTL input.
The NOT OUTPUT SELECT line only affects the chip when NOT CHIP ENABLE is low.
In BYTE mode, NOT CHIP ENABLE low to NOT OUTPUT SELECT low, (tsu) must be > 100nS to ensure
correct BYTE output sequence.
ON
SH (MIN)
SL (MIN)
OFF
CE (MIN)
CEDRH
FIG. 3 MULTICHANNEL ARINC 429 RECEIVER OUTPUT TIMING
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
Clock Period (500 - 800nS).
NOT CHIP ENABLE low to output active time.
NOT OUTPUT SELECT low to word valid time.
minimum NOT OUTPUT SELECT high time.
minimum NOT OUTPUT SELECT low time.
NOT CHIP ENABLE high to DATA READY low time.
NOT CHIP ENABLE high to data bus high impedance time. 20nS
minimum time NOT CHIP ENABLE high/low.
minimum time to select next word (CHIP ENABLE high
to DATA READY high).
7
Min
10nS
100nS
2.5T
4T + 20nS
MT34013
Max
250nS
300nS
400nS
400nS
2T + 500nS
100nS
6T + 300nS

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