sg2567udr212851hc ETC-unknow, sg2567udr212851hc Datasheet - Page 21

• Manufacturer Part Number: sg2567udr212851hc
• Description: Dram Module Ddr2 Sdram 2gbyte 240udimm
• Manufacturer: ETC-unknow

IDD Specification Parameters and Test Conditions (Contd.)
Notes:
1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Parametric Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#. IDD values must be met with all combinations of ERMS bits 10 and
5. Definitions for IDD
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11.
LOW
HIGH
STABLE
FLOATING
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for
= V
= V
= inputs stable at a HIGH or LOW level
= inputs at V
address and control signals, and inputs between HIGH and LOW every other data transfer
(once per clock) for DQ signals not including masks of strobes.
in
in
≤ V
≥ V
Parameter
CL(IDD)
t
t
t
t
t
t
t
t
RCD(IDD)
RC(IDD)
RRD(IDD)
CK(IDD)
RASmin(IDD)
RASmax(IDD)
RP(IDD)
RFC(IDD)
IL(AC)
IH(AC)
REF
(max)
(min)
= V
DDQ
IDD Testing Parameters
/2
DDR2-800
70000
127.5
5-5-5
12.5
57.5
12.5
7.5
2.5
45
5
SG2567UDR212851UU
Units
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
March 17, 2008
21