z16c32 ZiLOG Semiconductor, z16c32 Datasheet - Page 30

• Manufacturer Part Number: z16c32
• Description: Iusc Integrated Universal Serial Controller
• Manufacturer: ZiLOG Semiconductor

Z
PS97USC0200
ILOG
Address: 01001 (Shared)
Notes:
BDCR Controls the amount of time that DMA may remain bus master.
Bits 15 through 8 are used to select a limit for the number of DMA transfers on the Bus
while the DMA is bus master. This limit is a binary number, a value of zero disables
the transaction limit function.
Bits 7 through 0 are used to select a limit for the number of clock cycles that the DMA
may remain on the bus as bus master.
Bus transaction will always complete, even if the clock cycle limit is exceeded during
the bus cycle, and even if the cycle is extended by external hardware signalling
through /WAIT//RDY.
Figure 15. Burst Dwell Control Register (BDCR)
P R E L I M I N A R Y
Clock Cycle Limit (Bit 3)
Clock Cycle Limit (Bit 4)
Clock Cycle Limit (Bit 5)
Clock Cycle Limit (Bit 6)
Clock Cycle Limit (Bit 7)
Clock Cycle Limit (Bit 8)
Clock Cycle Limit (Bit 9)
Clock Cycle Limit (Bit 10)
Transaction Limit (Bit 0)
Transaction Limit (Bit 1)
Transaction Limit (Bit 2)
Transaction Limit (Bit 3)
Transaction Limit (Bit 4)
Transaction Limit (Bit 5)
Transaction Limit (Bit 6)
Transaction Limit (Bit 7)
Z16C32 IUSC
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