fw802a ETC-unknow, fw802a Datasheet - Page 8

• Manufacturer Part Number: fw802a
• Description: Low-power Ieee 1394a-2000 Two-cable Transceiver/arbiter Device
• Manufacturer: ETC-unknow

Two-Cable Transceiver/Arbiter Device
Signal Information
Table 1. Signal Descriptions (continued)
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
8 8
44, 45, 46,
47, 48
Pin
16
20
21
22
19
57
58
54
55
61
28
29
63
36
41
1
SYSCLK
/RESET
PLLV
Signal*
PLLV
TPA0+
TPA1+
LREQ
PC0
PC1
PC2
LPS
NC
SM
PD
SE
R0
R1
DD
SS
(continued)
Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted-
Type
—
—
—
O
I
I
I
I
I
I
I
I
Link Power Status. LPS is connected to either the V
LLC or to a pulsed output that is active when the LLC is powered for the
purpose of monitoring the LLC power status. If LPS is inactive for more
than 1.2 µs and less than 25 µs, interface is reset. If LPS is inactive for
greater than 25 µs, the PHY will disable the PHY/Link interface to save
power. FW802A continues its repeater function.
Link Request. LREQ is an output from the LLC that requests the PHY to
perform some service. Bus-keeper circuitry is built into this terminal.
No Connect.
Power-Class Indicators. On hardware reset, these inputs set the default
value of the power class indicated during self-ID. These bits can be
programmed by tying the signals to V
Powerdown. When asserted high, PD turns off all internal circuitry except
the bias-detect circuits that drive the CNA signal. Internal FW802A logic is
kept in the reset state as long as PD is asserted. PD terminal is provided
for backward compatibility. It is recommended that the FW802A be
allowed to manage its own power consumption using suspend/resume in
conjunction with LPS. C/LKON features are defined in 1394a-2000.
Power for PLL Circuit. PLLV
portion of the device.
Ground for PLL Circuit. PLLV
plane.
Current Setting Resistor. An internal reference voltage is applied to a
resistor connected between R0 and R1 to set the operating current and
the cable driver output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 kΩ ± 1% should be used to meet the
IEEE 1394-1995 standard requirements for output voltage limits.
Reset (Active-Low). When /RESET is asserted low (active), the FW802A
is reset. An internal pull-up resistor, which is connected to V
provided, so only an external delay capacitor is required. This input is a
standard logic buffer and can also be driven by an open-drain logic output
buffer.
Test Mode Control. SE is used during the manufacturing test and should
be tied to V
Test Mode Control. SM is used during the manufacturing test and should
be tied to V
System Clock. SYSCLK provides a 49.152 MHz clock signal, which is
synchronized with the data transfers to the LLC.
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
SS
SS
.
.
Name/Description
DD
SS
supplies power to the PLL circuitry
is tied to a low-impedance ground
DD
(high) or to ground (low).
DD
Agere Systems Inc.
supplying the
DD
June 2001
, is